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參數資料
| 型號： | CY74FCT163543TSSOP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16-Bit Latched Transceiver |
| 中文描述： | 16位鎖存器 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 64K |
| 代理商： | CY74FCT163543TSSOP |
16-Bit Latched Transceiver
CY74FCT163543
SCCS063A - June 1997 - Revised April 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
1CY74FCT163543
Features
Low power, pin-compatible replacement for LCX and
LPT families
5V tolerant inputs and outputs
24 mA balanced drive outputs
Power-off disable outputs permits live insertion
Edge-rate control circuitry for reduced noise
FCT-C speed at 5.1 ns
Latch-up performance exceeds JEDEC standard no. 17
ESD > 2000V per MIL-STD-883D, Method 3015
Typical output skew < 250 ps
Industrial temperature range of –40C to +85C
TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
Typical V
olp
(ground bounce) performance exceeds Mil
Std 883D
V
CC
= 2.7V to 3.6V
Functional Description
The CY74FCT163543 is a 16-bit, high-speed, low power latched
transceiverthatisorganizedastwoindependent8-bitD-typelatched
transceivers,containingtwosetsofeightD-typelatcheswithseparate
LatchEnable(LEAB,LEAB)andOutputEnable(OEAB,OEAB)con-
trols for each set to permit independent control of inputting and out-
putting in either direction of data flow. For data flow from A to B, for
example, the A-to-B input Enable (CEAB) must be LOW in order to
enterdatafromAortotakedatafromB,asindicatedinthetruthtable.
WithCAEBLOW,aLOWsignalontheA-to-BLatchEnable(LEAB)
makes the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the LEAB signal puts the A latches in the storage mode
andtheiroutputsnolongerfollowtheAinputs.WithCEABandOEAB
both LOW, the three-state B output buffers are active and reflect the
datapresent atthe output ofthe Alatches.Control ofdatafrom Bto
A is similar, but usesCEAB,LEAB, andOEAB inputs.
The CY74FCT163543 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The inputs
and outputs are capable of being driven by 5.0V buses, allow-
ing them to be used in mixed voltage systems as translators.
The outputs are also designed with a power off disable feature
enabling them to be used in applications requiring live inser-
tion. Flow-throughpinoutandsmallshrinkpackagingsimplifyboard
design.
Logic Block Diagrams
PinConfiguration
1
OEAB
1
LEAB
1
CEAB
SSOP/TSSOP
Top View
GND
1
A
1
1
A
2
V
CC
2
A
7
2
A
8
GND
2
CEAB
2
LEAB
TO 7 OTHER CHANNELS
D
C
1
B
1
1
OEBA
1
CEBA
1
LEBA
1
A
1
1
LEAB
1
OEAB
1
CEAB
D
C
D
C
2
B
1
2
OEBA
2
CEBA
2
LEBA
2
A
1
2
OEAB
2
CEAB
2
LEAB
V
CC
1
A
3
1
A
4
GND
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
2
A
3
1
A
5
GND
2
A
4
2
A
5
2
A
6
2
OEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEBA
1
LEBA
1
CEBA
GND
1
B
1
1
B
2
V
CC
2
B
7
2
B
8
GND
2
CEBA
2
LEBA
V
CC
1
B
3
1
B
4
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
1
B
5
GND
2
B
4
2
B
5
2
B
6
2
OEBA
D
C
TO 7 OTHER CHANNELS
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相關代理商/技術參數 |
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