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參數資料
| 型號： | CY74FCT165000T |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 18-Bit Registered Transceivers |
| 中文描述： | 18位注冊收發器 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 63K |
| 代理商： | CY74FCT165000T |
18-Bit Registered Transceivers
CY74FCT16500T
CY74FCT162500T
SCCS056 - August 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
FCT-C speed at 4.6 ns
Power-off disable outputs permits live insertion
Edge-rate control circuitry for significantly improved
noise characteristics
Typical output skew < 250 ps
ESD > 2000V
TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
Industrial temperature range of
40C to +85C
V
CC
= 5V
±
10%
CY74FCT16500T Features:
64 mA sink current, 32 mA source current
Typical V
OLP
(ground bounce) <1.0V at V
CC
= 5V,
T
A
= 25C
CY74FCT162500T Features:
Balanced 24 mA output drivers
Reduced system switching noise
Typical V
OLP
(ground bounce) <0.6V at V
CC
= 5V,
T
A
= 25C
Functional Description
These 18-bit universal bus transceivers can be operated in
transparent, latched, or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output-enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA)
inputs. For A-to-B data flow, the device operates in transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CLKAB is held at a HIGH or LOW logic level. If LEAB
is LOW, the A bus data is stored in the latch/flip-flop on the
HIGH-to-LOW transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and
CLKBA. The output buffers are designed with power-off
disable feature that allows live insertion of boards.
The
CY74FCT16500T
is
high-capacitance loads and low-impedance backplanes.
The CY74FCT162500T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162500T is ideal for driving transmission lines.
ideally
suited
for
driving
GND
B
2
B
3
V
CC
LogicBlockDiagram
Pin Configuration
SSOP/TSSOP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
33
32
31
30
29
36
35
34
OEAB
LEAB
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
45
44
43
42
41
37
38
39
40
48
47
46
A
1
A
2
A
3
B
1
GND
CLKAB
GND
GND
B
7
B
8
B
9
B
10
V
CC
A
4
A
5
A
6
A
7
A
8
A
9
B
4
B
5
B
6
GND
A
10
A
11
A
12
GND
A
13
B
11
B
12
GND
B
13
GND
V
CC
A
16
A
17
GND
A
18
A
14
A
15
V
CC
B
16
B
17
GND
B
18
CLKBA
FCT16500-1
TO 17 OTHER CHANNELS
LEAB
OEBA
LEBA
CLKAB
CLKBA
OEAB
C
D
C
D
C
D
C
D
A
1
B
1
49
52
51
50
OEBA
LEBA
53
56
55
54
B
14
B
15
FCT16500-2
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PDF描述 |
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| CY74FCT162841CTPAC | 20-Bit Latches |
| CY74FCT162H952TSSOP | 16-Bit Registered Transceivers |
| CY74FCT163373SSOP | 16-Bit Latch |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY74FCT16500CTPACT | 功能描述:總線收發器 18B Univ Bus Xceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| CY74FCT16500CTPVC | 功能描述:通用總線函數 18B Universal Bus Transceivers RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| CY74FCT16500CTPVCT | 功能描述:通用總線函數 18B Universal Bus Transceivers RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| CY74FCT16500T | 制造商:TI 制造商全稱:Texas Instruments 功能描述:18-Bit Registered Transceivers |
| CY74FCT16500T_08 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:18-Bit Registered Transceivers |
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