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參數(shù)資料
型號: CY74FCT823ATSOCTG4
廠商: Texas Instruments
文件頁數(shù): 1/15頁
文件大?。?/td> 0K
描述: IC 9BIT BUS INT F-F 3ST 24-SOIC
標(biāo)準(zhǔn)包裝: 2,000
系列: 74FCT
功能: 主復(fù)位
類型: D 型總線
輸出類型: 三態(tài)非反相
元件數(shù): 1
每個元件的位元數(shù): 9
延遲時間 - 傳輸: 6ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 32mA,64mA
電源電壓: 4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
CY74FCT823T
9-BIT BUS-INTERFACE REGISTER
WITH 3-STATE OUTPUTS
SCCS069A – OCTOBER 2001 – REVISED NOVEMBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Function, Pinout, and Drive Compatible
With FCT, F Logic, and AM29823
D Reduced VOH (Typically = 3.3 V) Version of
Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D Fully Compatible With TTL Input and
Output Logic Levels
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D 64-mA Output Sink Current
32-mA Output Source Current
D High-Speed Parallel Register With
Positive-Edge-Triggered D-Type Flip-Flops
D Buffered Common Clock-Enable (EN) and
Asynchronous-Clear (CLR) Inputs
D 3-State Outputs
description
This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a
9-bit-wide buffered register with clock-enable (EN) and clear (CLR) inputs that are ideal for parity bus interfacing
in high-performance microprogrammed systems. It is ideal for use as an output port requiring high IOL/IOH.
This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading
at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Copyright
2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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24
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OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
CLR
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN
CP
P, Q, OR SO PACKAGE
(TOP VIEW)
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