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參數資料
| 型號： | CY74FCT841T |
| 英文描述： | 10-Bit Bus-Interface D-Type Latches with 3-State Outputs |
| 中文描述： | 10 - 3位總線接口D類鎖存態輸出 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 102K |
| 代理商： | CY74FCT841T |
CY74FCT823T
9-BIT BUS-INTERFACE REGISTER
SCCS069 – OCTOBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Function, Pinout, and Drive Compatible
With FCT, F Logic, and AM29823
Reduced V
OH
(Typically = 3.3 V) Version of
Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
I
off
Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
64-mA Output Sink Current
32-mA Output Source Current
High-Speed Parallel Register With
Positive-Edge-Triggered D-Type Flip-Flops
Buffered Common Clock-Enable (EN) and
Asynchronous-Clear (CLR) Inputs
description
This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a
9-bit-wide buffered register with clock-enable (EN) and clear (CLR) inputs that are ideal for parity bus interfacing
in high-performance microprogrammed systems. This device is ideal for use as an output port requiring high
I
OL
/I
OH
.
This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading
at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
PIN DESCRIPTION
NAME
I/O
DESCRIPTION
D
I
D flip-flop data inputs
CLR
I
When CLR is low and OE is low, Q outputs are low. When CLR is high, data can be entered into the register.
CP
O
Clock pulse for the register. Enters data into the register on the low-to-high clock transition.
Y
O
Register 3-state outputs
EN
I
Clock enable. When EN is low, data on the D input is transferred to the Q output on the low-to-high clock transition. When
EN is high, the Q outputs do not change state, regardless of the data or clock input transitions.
OE
I
Output control. When OE is high, the Y outputs are in the high-impedance state. When OE is low, true register data is present
at the Y outputs.
Copyright
2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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10
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12
24
23
22
21
20
19
18
17
16
15
14
13
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
CLR
GND
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
EN
CP
P, Q, OR SO PACKAGE
(TOP VIEW)
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