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參數(shù)資料
| 型號(hào)： | CY7B994V |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | High-Speed Multi-Phase PLL Clock Buffer(高速多相位PLL時(shí)鐘緩沖器) |
| 中文描述： | 7B SERIES, PLL BASED CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 1/15頁(yè) |
| 文件大小： | 390K |
| 代理商： | CY7B994V |
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High-speed Multi-phase PLL Clock Buffer
Functional Description
RoboClock
CY7B993V
CY7B994V
Cypress Semiconductor Corporation
Document #: 38-07127 Rev. *F
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised August 10, 2005
Features
500-ps max. Total Timing Budget (TTB) window
12–100-MHz (CY7B993V), or 24–200-MHz (CY7B994V)
input/output operation
Matched pair output skew < 200 ps
Zero input-to-output delay
18 LVTTL outputs driving 50
terminated lines
16 outputs at 200 MHz: Commercial temperature
6 outputs at 200 MHz: Industrial temperature
3.3V LVTTL/LVPECL, fault-tolerant, and hot insertable
reference inputs
Phase adjustments in 625-/1300-ps steps up to ± 10.4 ns
Multiply/divide ratios of 1–6, 8, 10, 12
Individual output bank disable
Output high-impedance option for testing purposes
Fully integrated phase-locked loop (PLL) with lock
indicator
<50-ps typical cycle-to-cycle jitter
Single 3.3V ± 10% supply
100-pin TQFP package
100-lead BGA package
The CY7B993V and CY7B994V High-speed Multi-phase PLL
Clock Buffers offer user-selectable control over system clock
functions. This multiple-output clock driver provides the
system integrator with functions necessary to optimize the
timing of high-performance computer and communication
systems.
These devices feature a guaranteed maximum TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Eighteen configurable outputs each drive terminated trans-
mission lines with impedances as low as 50
while delivering
minimal and specified output skews at LVTTL levels. The outputs
are arranged in five banks. Banks 1 to 4 of four outputs allow
a divide function of 1 to 12, while simultaneously allowing
phase adjustments in 625–1300-ps increments up to 10.4 ns.
One of the output banks also includes an independent clock
invert function. The feedback bank consists of two outputs,
which allows divide-by functionality from 1 to 12 and limited
phase adjustments. Any one of these eighteen outputs can be
connected to the feedback input as well as driving other inputs.
Selectable reference input is a fault tolerance feature that
allows smooth change-over to secondary clock source, when
the primary clock source is not in operation. The reference
inputs and feedback inputs are configurable to accommodate
both LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
FS
OUTPUT_MODE
FBF0
FBDS0
FBDS1
FBDIS
4F0
4F1
4DS0
4DS1
DIS4
3F0
3F1
3DS0
3DS1
DIS3
INV3
2F0
2F1
2DS0
2DS1
DIS2
1F0
1F1
1DS0
1DS1
DIS1
QFA0
QFA1
4QA0
4QA1
4QB0
4QB1
3QA0
3QA1
3QB0
3QB1
2QA0
2QA1
2QB0
2QB1
1QA0
1QA1
1QB0
1QB1
LOCK
FBKA+
FBKA–
FBKB+
FBKB–
FBSEL
REFA+
REFA–
REFB+
REFB–
REFSEL
3
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Phase
Freq.
Detector
Filter
VCO
Control Logic
Divide and Phase
Generator
Feedback Bank
Bank 4
Bank 3
Bank 2
Bank 1
Functional
Block Diagram
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PDF描述 |
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| CY7C008V-15AC | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; No. of Contacts:55; Connector Shell Size:23; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight |
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| CY7C008V-20AC | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; No. of Contacts:55; Connector Shell Size:23; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight |
| CY7C008V-25AC | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; No. of Contacts:55; Connector Shell Size:23; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B994V-2AC | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 24MHz to 200MHz 100-Pin TQFP |
| CY7B994V-2ACT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High-speed Multi-phase PLL Clock Buffer |
| CY7B994V-2AI | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 24MHz to 200MHz 100-Pin TQFP |
| CY7B994V-2AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High-speed Multi-phase PLL Clock Buffer |
| CY7B994V-2AXC | 功能描述:鎖相環(huán) - PLL 3.3V 200MHz 10 COM Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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