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參數資料
| 型號： | CY7C0430V-100BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | LED Ring Light; LED Color:Red; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:500mA; Supply Voltage:24VDC; Wavelength:630nm |
| 中文描述： | 64K X 18 FOUR-PORT SRAM, 5 ns, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, 1.27 MM PITCH, BGA-272 |
| 文件頁數： | 1/36頁 |
| 文件大?。?/td> | 935K |
| 代理商： | CY7C0430V-100BGC |
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PRELIMINARY
3.3V 64K x 18
Synchronous QuadPort Static RAM
CY7C0430V
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
November 18, 1999
30V
Features
True four-ported memory cells which allow simulta-
neous access of the same memory location
Synchronous Pipelined device
—64K x 18 organization
Pipelined output mode allows fast 133-MHz operation
High Bandwidth up to 10 Gbps (133 MHz x 18 bits wide
x 4 ports)
0.25-micron CMOS for optimum speed/power
High-speed clock to data access 4.7 ns (max.)
3.3V Low operating power
—Active = 750mA (maximum)
—Standby = 1mA (maximum)
Counter wrap-around control
—Internal mask register controls counter wrap-around
—Counter-Interrupt flags to indicate wrap-around
Counter readback on address lines
Mask register readback on address lines
Interrupt flags for message passing
Master reset for all ports
Width and depth expansion capabilities
Dual Chip Enables on all ports for easy depth expansion
Separate upper-byte and lower-byte controls on all
ports
272-BGA package (27 mm x 27 mm 1.27 mm ball pitch)
Commercial and Industrial temperature ranges
IEEE 1149.1 JTAG boundary scan
BIST (Built In Self Test) controller
Notes:
1.
2.
Port 1 Control Logic Block is detailed on page 2.
Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
Port-1
Control
Logic
Port 1
Counter/
Mask Reg/
Address
Decode
Port 1
I/O
18
Top Level Logic Block Diagram
RAM
Array
Port 1 Operation-Control Logic Blocks
[1]
Port 2 Logic Blocks
[2]
Port 4 Logic Blocks
[2]
Port 3 Logic Blocks
[2]
CNTLD
P1
CNTINC
P1
CNTRD
P1
CNTRST
P1
INT
P1
MKLD
P1
CNTINT
P1
MKRD
P1
CE
1P1
CE
0P1
R/W
P1
OE
P1
UB
P1
LB
P1
I/O
0P1
- I/O
17P1
A
0P1
–A
15P1
16
TMS
TCK
TDI
TDO
BIST
MRST
Reset
Logic
JTAG
Controller
CLK
P1
CLK
P1
CLKBIST
Port 1
Port 2
Port 3
Port 4
For the most recent information, visit the Cypress web site at www.cypress.com
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C0430V-100BGI | Linear Array Light; LED Color:Red; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:800mA; Supply Voltage:24VDC; Wavelength:627nm |
| CY7C0430V-133BGC | 3.3V 64K x 18 Synchronous QuadPort⑩ Static RAM |
| CY7C0430V-133BGI | 3.3V 64K x 18 Synchronous QuadPort⑩ Static RAM |
| CY7C056V-12BBC | 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM |
| CY7C056V-15BBC | 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C0430V-100BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 64K x 18 Synchronous QuadPort⑩ Static RAM |
| CY7C0430V-133BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 64K x 18 Synchronous QuadPort⑩ Static RAM |
| CY7C0430V-133BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 64K x 18 Synchronous QuadPort⑩ Static RAM |
| CY7C04312BV | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:10 Gb/s 3.3V QuadPort DSE Family |
| CY7C04312BV-100 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:10 Gb/s 3.3V QuadPort DSE Family |
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