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參數資料
| 型號： | CY7C1011CV33-12BVC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 128K x 16 Static RAM |
| 中文描述： | 128K X 16 STANDARD SRAM, 12 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, VFBGA-48 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 339K |
| 代理商： | CY7C1011CV33-12BVC |
128K x 16 Static RAM
CY7C1011CV33
Cypress Semiconductor Corporation
Document #: 38-05232 Rev. *B
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised October 10, 2002
Features
Pin equivalent to CY7C1011BV33
High speed
—t
AA
= 10 ns
Low active power
—360 mW (max.)
Data Retention at 2.0
Automatic power-down when deselected
Independent control of upper and lower bits
Easy memory expansion with CE and OE features
Available in 44-pin TSOP II, 44-pin TQFP, and 48-ball
VFBGA
Functional Description
The CY7C1011CV33 is a high-performance CMOS Static
RAM organized as 131,072 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
to I/O
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011CV33 is available in a standard 44-pin TSOP
II package with center power and ground pinout, a 44-pin Thin
Plastic Quad Flatpack (TQFP), as well as a 48-ball fine-pitch
ball grid array (VFBGA) package.
1
A
1
A
Logic Block Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
S
INPUT BUFFER
256K x 16
ARRAY
1024 x 4096
A
0
A
1
A
1
A
1
A
1
A
9
A
1
I/O
0
–
I/O
7
OE
BLE
I/O
8
–
I/O
15
CE
BHE
A
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
TSOP II
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
4
I/O
5
A
15
A
14
A
13
A
12
A
4
A
3
A
2
A
1
A
0
OE
BHE
BLE
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
A
5
A
6
A
7
I/O
15
I/O
14
I/O
13
I/O
12
CE
I/O
0
I/O
1
I/O
2
I/O
3
NC
A
8
A
9
A
10
A
11
18
19
20
21
27
26
25
24
22
23
NC
I/O
6
IWE
7
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1011CV33-12BVI | 128K x 16 Static RAM |
| CY7C1011CV33-12ZC | 128K x 16 Static RAM |
| CY7C1011CV33-12ZI | 128K x 16 Static RAM |
| CY7C1011BV33 | 128K x 16 Static RAM |
| CY7C1011BV33-12ZC | 128K x 16 Static RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C1011CV33-12BVI | 制造商:Rochester Electronics LLC 功能描述:2MB (128KX16) FAST ASYNCH SRAM 3.3V - Bulk |
| CY7C1011CV33-12BVIT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1011CV33-12XEKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1011CV33-12ZC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1011CV33-12ZI | 制造商:Rochester Electronics LLC 功能描述:2MB (128KX16) FAST ASYNCH SRAM 3.3V - Bulk |
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