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參數資料
| 型號： | CY7C10211B-10VC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1-Mbit (64K x 16) Static RAM |
| 中文描述： | 64K X 16 STANDARD SRAM, 10 ns, PDSO44 |
| 封裝： | 0.400 INCH, SOJ-44 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 370K |
| 代理商： | CY7C10211B-10VC |
1-Mbit (64K x 16) Static RAM
CY7C1021B
CY7C10211B
Cypress Semiconductor Corporation
Document #: 38-05145 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised June 20, 2004
Features
Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
High speed
— t
AA
= 10 ns (Commercial & Industrial)
— t
AA
= 15 ns (Automotive)
CMOS for optimum speed/power
Low active power
— 825 mW (max.)
Automatic power-down when deselected
Independent control of upper and lower bits
Available in 44-pin TSOP II and 400-mil SOJ
Also available in Lead (Pb)-Free 44-pin TSOP II
Functional Description
[1]
The CY7C1021B/10211B is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
9
to I/O
16
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1021B/10211B is available in standard 44-pin
TSOP Type II and 400-mil-wide SOJ packages. Customers
should use part number CY7C10211B when ordering parts
with 10-ns t
AA
, and CY7C1021B when ordering 12- and 15-ns
t
AA
.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
64K x 16
RAM Array
512 X 2048
I/O
1
–I/O
8
R
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
A
9
A
1
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
I/O
9
–I/O
16
CE
WE
BHE
A
8
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C10211B-10ZC | 1-Mbit (64K x 16) Static RAM |
| CY7C10211BL-10ZC | 1-Mbit (64K x 16) Static RAM |
| CY7C1021B-12VC | 1-Mbit (64K x 16) Static RAM |
| CY7C1021B-12VI | 1-Mbit (64K x 16) Static RAM |
| CY7C1021B-12ZC | 1-Mbit (64K x 16) Static RAM |
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