
PRELIMINARY
32K x 16 Static RAM
CY7C1022
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
April 6, 1998
Y7C10
Features
5.0V operation (± 10%)
High speed
—t
AA
= 12 ns
Low active power
—825 mW (max., 10 ns, “L” version)
Very Low standby power
—500
μ
W (max., “L” version)
Automatic power-down when deselected
Independent Control of Upper and Lower bytes
Available in 400-mil SOJ
Functional Description
The CY7C1022 is a high-performance CMOS static RAM or-
ganized as 32,768 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking chip enable
(CE) input HIGH and write enable (WE) input LOW. If byte low
enable (BLE) is LOW, then data from I/O pins (I/O
1
through
I/O
8
), is written into the location specified on the address pins
(A
0
through A
14
). If byte high enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
14
).
Reading from the device is accomplished by taking chip en-
able (CE) HIGH and output enable (OE) LOW while forcing the
write enable (WE) HIGH. If byte low enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
1
to I/O
8
. If byte high enable (BHE) is LOW,
then data from memory will appear on I/O
9
to I/O
16
. See the
truth table at the back of this datasheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
HIGH, and WE LOW).
The CY7C1022 is available in standard 400-mil-wide SOJ
packages.
2CY7C1022
Selection Guide
WE
A
10
A
9
A
8
A
7
NC
Logic Block Diagram
Pin Configuration
SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
5
I/O
6
NC
A
14
A
13
A
12
A
11
CE
OE
BHE
BLE
V
SS
V
CC
I/O
12
I/O
11
I/O
10
I/O
9
A
0
A
1
A
2
I/O
16
I/O
15
I/O
14
I/O
13
I/O
3
I/O
4
I/O
1
I/O
2
NC
A
3
A
4
A
5
A
6
1022-2
18
19
20
21
27
26
25
24
22
23
NC
I/O
7
I/O
8
32K x 16
RAM Array
I/O
1
– I/O
8
R
A
6
A
5
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
A
9
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
BLE
I/O
9
– I/O
16
OE
WE
A
8
A
7
7C1022-12
12
170
140
3
0.1
7C1022-15
15
160
130
3
0.1
Maximum Access Time (ns)
Maximum Operating Current (mA)
L
Maximum CMOS Standby Current (mA)
L
Shaded areas contain advance information.