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參數資料
| 型號： | CY7C1041BL-15ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K x 16 Static RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 15 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 360K |
| 代理商： | CY7C1041BL-15ZC |
256K x 16 Static RAM
CY7C1041B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
March 23, 2001
1CY7C1041B
Features
High speed
—
t
AA
= 12 ns
Low active power
—
1540 mW (max.)
Low CMOS standby power (L version)
—
2.75 mW (max.)
2.0V Data Retention (400
μ
W at 2.0V retention)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Functional Description
The CY7C1041B is a high-performance CMOS static RAM or-
ganized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O
8
to I/O
15
. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041B is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
1
A
1
A
Logic Block Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
S
INPUT BUFFER
256K x 16
ARRAY
1024 x 4096
A
0
A
1
A
1
A
1
A
1
A
1
1041B–2
A
9
A
1
I/O
0
– I/O
7
BLE
I/O
8
– I/O
15
OE
WE
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
SOJ
TSOP II
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
4
I/O
5
A
0
A
1
A
2
A
3
A
4
OE
BHE
BLE
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
17
A
16
A
15
I/O
15
I/O
14
I/O
13
I/O
12
CE
I/O
0
I/O
1
I/O
2
I/O
3
18
19
20
21
27
26
25
24
22
23
I/O
6
I/O
7
A
14
A
13
A
12
A
11
A
10
1041B–1
Selection Guide
7C1041B-12
12
200
220
3
-
-
7C1041B-15
15
190
210
3
0.5
6
7C1041B-17
17
180
200
3
0.5
6
7C1041B-20
20
170
190
3
0.5
6
7C1041B-25
25
160
180
3
0.5
6
Maximum Access Time (ns)
Maximum Operating Current (mA) Com’l
Ind’l
Com’l
Com’l
Ind’l
Maximum CMOS Standby Current
(mA)
L
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|---|---|
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