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參數(shù)資料
| 型號： | CY7C1051DV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8-Mbit (512K x 16) Static RAM |
| 中文描述： | 8兆位（為512k × 16）靜態(tài)RAM |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 500K |
| 代理商： | CY7C1051DV33 |
PRELIMINARY
8-Mbit (512K x 16) Static RAM
CY7C1051DV33
Cypress Semiconductor Corporation
Document #: 001-00063 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised March 9, 2007
Features
High speed
— t
AA
= 10 ns
Low active power
— I
CC
= 110 mA @ 10 ns
Low CMOS standby power
— I
SB2
= 20 mA
2.0V data retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in lead-free 48-ball FBGA and 44-pin TSOP II
packages
Functional Description
[1]
The CY7C1051DV33 is a high-performance CMOS Static
RAM organized as 512K words by 16 bits.
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW,
then data from IO pins (IO
0
–IO
7
), is written into the location
specified on the address pins (A
0
–A
18
). If Byte HIGH Enable
(BHE) is LOW, then data from IO pins (IO
8
–IO
15
) is written into
the location specified on the address pins (A
0
–A
18
).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte LOW Enable (BLE) is LOW, then data from the memory
location specified by the address pins will appear on IO
0
–IO
7
.
If Byte HIGH Enable (BHE) is LOW, then data from memory
will appear on IO
8
to IO
15
. See the
“Truth Table” on page 8
for
a complete description of Read and Write modes.
The input/output pins (IO
0
–IO
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or a Write operation (CE LOW,
and WE LOW) is in progress.
The CY7C1051DV33 is available in a 44-pin TSOP II package
with center power and ground (revolutionary) pinout, as well
as a 48-ball fine-pitch ball grid array (FBGA) package.
Note
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at
www.cypress.com
.
1
A
1
A
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
S
INPUT BUFFER
512K × 16
ARRAY
A
0
A
1
A
1
A
1
A
1
A
1
A
1
A
9
A
1
IO
0
–IO
7
OE
BLE
IO
8
–IO
15
CE
WE
BHE
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1051DV33-10BAXI | 功能描述:靜態(tài)隨機(jī)存取存儲器 8MB (512Kx16) 3.3v 10ns Fast Async 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1051DV33-10BAXIT | 功能描述:靜態(tài)隨機(jī)存取存儲器 8M FAST ASYNC HI SPD 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1051DV33-10ZSXI | 功能描述:靜態(tài)隨機(jī)存取存儲器 8M FAST ASYNC IND HI SPD 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1051DV33-10ZSXI | 制造商:Cypress Semiconductor 功能描述:IC SRAM 8Mbit 10ns 44-TSOP 制造商:Cypress Semiconductor 功能描述:IC, SRAM, 8Mbit, 10ns, 44-TSOP |
| CY7C1051DV33-10ZSXIT | 功能描述:靜態(tài)隨機(jī)存取存儲器 8M FAST ASYNC HI SPD 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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