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參數資料
| 型號： | CY7C106B-35VI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Crimp; Body Material:Aluminum; Series:PT06; No. of Contacts:15; Connector Shell Size:14; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight |
| 中文描述： | 256K X 4 STANDARD SRAM, 35 ns, PDSO28 |
| 封裝： | 0.400 INCH, SOJ-28 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 161K |
| 代理商： | CY7C106B-35VI |
256K x 4 Static RAM
CY7C106B
CY7C1006B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05037 Rev. **
Revised August 24, 2001
1CY7C1006B
Features
High speed
—tAA = 12 ns
CMOS for optimum speed/power
Low active power
— 495 mW
Low standby power
— 275 mW
2.0V data retention (optional)
— 100
W
Automatic power-down when deselected
TTL-compatible inputs and outputs
Functional Description
The CY7C106B and CY7C1006B are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE), an active LOW Output Enable (OE), and
three-state drivers. These devices have an automatic pow-
er-down feature that reduces power consumption by more
than 65% when the devices are deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O0 through I/O3) is then written into the location speci-
fied on the address pins (A0 through A17).
Reading from the devices is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the four I/O pins.
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE and WE LOW).
The CY7C106B is available in a standard 400-mil-wide SOJ;
the CY7C1006B is available in a standard 300-mil-wide SOJ.
Logic Block Diagram
Pin Configuration
C106B–1
C106B–2
512 x 512 x 4
ARRAY
A1
A
0
A
10
A
12
A
11
A
13
A
14
COLUMN
DECODER
R
O
W
DE
CODE
R
S
E
N
S
E
AM
PS
POWER
DOWN
OE
INPUT BUFFER
A
15
A
16
A
17
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
SOJ
12
13
25
28
27
26
GND
A1
A2
A3
A4
A5
A6
A7
A8
A17
VCC
A16
A15
A14
A13
I/O3
I/O2
I/O1
I/O0
A9
A0
A10
CE
OE
NC
A12
A11
WE
CE
I/O0
I/O1
I/O2
I/O3
A2
A3
A4
A6
A7
A8
A9
A5
Selection Guide
7C106B-12
7C1006B-12
7C106B-15
7C1006B-15
7C106B-20
7C1006B-20
7C106B-25
7C1006B-25
7C106B-35
Maximum Access Time (ns)
12
15
20
25
35
Maximum Operating
Current (mA)
90
80
75
70
60
Maximum Standby
Current (mA)
50
30
25
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