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參數資料
| 型號： | CY7C109-25ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 128K x 8 Static RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 25 ns, PDSO32 |
| 封裝： | TSOP1-32 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 220K |
| 代理商： | CY7C109-25ZC |
128K x 8 Static RAM
CY7C109
CY7C1009
Cypress Semiconductor Corporation
Document #: 38-05032 Rev. **
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised August 24, 2001
009
Features
High speed
—t
AA
= 10 ns
Low active power
—1017 mW (max., 12 ns)
Low CMOS standby power
—55 mW (max.), 4 mW (Low power version)
2.0V Data Retention (Low power version)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and OE options
Functional Description
The CY7C109 / CY7C1009 is a high-performance CMOS stat-
ic RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW chip enable (CE
1
), an
active HIGH chip enable (CE
2
), an active LOW output enable
(OE), and three-state drivers. Writing to the device is accom-
plished by taking chip enable one (CE
1
) and write enable (WE)
inputs LOW and chip enable two (CE
2
) input HIGH. Data on
the eight I/O pins (I/O
0
through I/O
7
) is then written into the
location specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking chip en-
able one (CE
1
) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C109 is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009 is available in
a 300-mil-wide SOJ package. The CY7C1009 and CY7C109
are functionally equivalent in all other respects.
1
A
1
A
Logic Block Diagram
Pin Configurations
SOJ
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
2
I/O
1
I/O
2
I/O
3
512 x 256 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
CE
1
A
1
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
19
18
20
24
23
22
21
25
28
27
26
Top View
29
32
31
30
16
17
GND
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
WE
A
13
A
8
A
9
A
11
V
CC
A
15
CE
2
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
109
–
1
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A
10
109
–
2
A
6
A
5
A
7
A
16
A
14
A
12
WE
CE
2
A
15
V
NC
A
4
A
13
A
8
A
9
OE
A
10
TSOP I
Top View
(not to scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
I/O
2
I/O
1
I/O
0
A
0
GND
I/O
7
I/O
6
I/O
4
I/O
3
I/O
5
CE
A
11
17
A
1
A
2
A
3
109
–
3
Selection Guide
7C109-10
7C1009-10
10
195
10
2
7C109-12
7C1009-12
12
185
10
2
7C109-15
7C1009-15
15
155
10
2
7C109-20
7C1009-20
20
140
10
—
7C109-25
7C1009-25
25
135
10
—
7C109-35
7C1009-35
35
125
10
—
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Maximum CMOS Standby Current (mA)
Low Power Version
Shaded areas contain preliminary information.
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