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參數資料
| 型號： | CY7C109BN-12ZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 128K x 8 Static RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 12 ns, PDSO32 |
| 封裝： | 8 X 20 MM, LEAD FREE, TSOP1-32 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 452K |
| 代理商： | CY7C109BN-12ZXC |
128K x 8 Static RAM
CY7C109BN
CY7C1009BN
Cypress Semiconductor Corporation
Document #: 001-06430 Rev. **
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised February 1, 2006
Features
High speed
— t
AA
= 12 ns
Low active power
— 495 mW (max. 12 ns)
Low CMOS standby power
— 55 mW (max.) 4 mW
2.0V Data Retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and OE options
Functional Description
[1]
The CY7C109BN/CY7C1009BN is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE
1
), an active HIGH Chip Enable (CE
2
), an active LOW
Output Enable (OE), and three-state drivers. Writing to the
device is accomplished by taking Chip Enable One (CE
1
) and
Write Enable (WE) inputs LOW and Chip Enable Two (CE
2
)
input HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is
then written into the location specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable One (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE
2
) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C109BN is available in standard 400-mil-wide SOJ
and 32-pin TSOP type I packages. The CY7C1009BN is
available in a 300-mil-wide SOJ package. The CY7C1009BN
and CY7C109BN are functionally equivalent in all other
respects.
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
1
A
1
A
Logic Block Diagram
Pin Configurations
SOJ
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
2
I/O
1
I/O
2
I/O
3
512 x 256 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
CE
1
A
1
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
19
18
20
24
23
22
21
25
28
27
26
Top View
29
32
31
30
16
17
GND
A
16
A
14
A
12
A7
A6
A5
A4
A3
A2
A1
A0
WE
A
13
A
8
A
9
A
11
V
CC
A
15
CE
2
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A
10
A
6
A
5
A
7
A
16
A
14
A
12
WE
CE
2
A
15
V
NC
A
4
A
13
A
8
A
9
OE
A
10
TSOP I
Top View
(not to scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
I/O
2
I/O
1
I/O
0
A
0
GND
I/O
7
I/O
6
I/O
4
I/O
3
I/O
5
CE
A
11
17
A
1
A
2
A
3
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| CY7C109BN-15VI | 128K x 8 Static RAM |
| CY7C109BN-15ZC | 128K x 8 Static RAM |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C109BN-12ZXCT | 功能描述:IC SRAM 1MBIT 12NS 32TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C109BN-15VC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY7C109BN-15VCT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C109BN-15VI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 1M-Bit 128K x 8 15ns 32-Pin SOJ |
| CY7C109BN-15VIT | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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