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參數(shù)資料
| 型號： | CY7C109V33L-25VC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 128K x 8 Static RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 25 ns, PDSO32 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-32 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 210K |
| 代理商： | CY7C109V33L-25VC |
128K x 8 Static RAM
memory expansion is provided by an active LOW Chip Enable
(CE
1
), an active HIGH Chip Enable (CE
2
), an active LOW Out-
put Enable (OE), and three-state drivers. Writing to the device
is accomplished by taking Chip Enable one (CE
1
) and Write
Enable (WE) inputs LOW and Chip Enable two (CE
2
) input
HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then
written into the location specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip En-
able one (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C109V33 is available in standard 32-pin,
400-mil-wide SOJ package. The CY7C1009V33 is available in
a 32-pin, 300-mil-wide SOJ package. The CY7C1009V33 and
CY7C109V33 are functionally equivalent in all other respects.
CY7C1009V33
CY7C109V33
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
September 3, 1999
Features
High speed
—t
AA
= 15, 20, 25ns
V
CC
= 3.3V ± 10%
Low active power
—432 mW (max.)
—288 mW (L version)
Low CMOS standby power
—18 mW (max.)
—7.2 mW (L version)
2.0V Data Retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and OE options
Functional Description
The CY7C109V33/CY7C1009V33 is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
Logic Block Diagram
Shaded areas contain preliminary information.
Selection Guide
7C109V33-12
7C1009V33-12
12
130
90
5
2
7C109V33-15
7C1009V33-15
15
120
80
5
2
7C109V33-20
7C1009V33-20
20
110
70
5
2
7C109V33-25
7C1009V33-25
20
110
70
5
2
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Operating Current (mA) Low Power Version
Maximum CMOS Standby Current (mA) Standard
Maximum CMOS Standby Current (mA) Low Power Version
1
A
1
A
Pin Configurations
SOJ
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
2
I/O
1
I/O
2
I/O
3
512 x 256 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
CE
1
A
1
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
19
18
20
24
23
22
21
25
28
27
26
Top View
29
32
31
30
16
17
GND
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
WE
A
13
A
8
A
9
A
11
V
CC
A
15
CE
2
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
109V33–1
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A
10
109V33–2
A
6
A
5
A
7
A
16
A
14
A
12
WE
2
A
15
V
CC
NC
A
4
A
13
A
8
A
9
OE
A
10
TSOP I
Top View
(not to scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
I/O
1
I/O
0
A
0
I/O
I/O
7
I/O
6
4
I/O
3
I/O
5
CE
A
11
17
A
1
A
2
A
3
109V33–3
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