- 您現在的位置：買賣IC網 > PDF目錄380186 > CY7C1217H-100AXC (CYPRESS SEMICONDUCTOR CORP) 1-Mbit (32K x 36) Flow-Through Sync SRAM PDF資料下載
參數資料
| 型號： | CY7C1217H-100AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1-Mbit (32K x 36) Flow-Through Sync SRAM |
| 中文描述： | 32K X 36 CACHE SRAM, 8 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 362K |
| 代理商： | CY7C1217H-100AXC |
CY7C1217H
1-Mbit (32K x 36) Flow-Through Sync SRAM
Cypress Semiconductor Corporation
Document #: 38-05670 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised July 6, 2006
Features
32K x 36 common I/O
3.3V core power supply (V
DD
)
2.5V/3.3V I/O power supply (V
DDQ
)
Fast clock-to-output times
— 6.5 ns (for 133-MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Available in JEDEC-standard lead-free 100-Pin TQFP
package
“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1217H is a 32K x 36 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:D]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1217H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1217H operates from a +3.3V core power supply
while all outputs may operate either with a +2.5V or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz
6.5
225
40
100 MHz
8.0
205
40
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1217H-100AXI | 1-Mbit (32K x 36) Flow-Through Sync SRAM |
| CY7C1217H-133AXC | 1-Mbit (32K x 36) Flow-Through Sync SRAM |
| CY7C1217H-133AXI | 1-Mbit (32K x 36) Flow-Through Sync SRAM |
| CY7C1218H | 1-Mbit (32K x36) Pipelined Sync SRAM |
| CY7C1218H-100AXC | 1-Mbit (32K x36) Pipelined Sync SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C1217H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 1.125MBIT 32KX36 7.5NS 100TQFP - Bulk |
| CY7C1218H-133AXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1218H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 1.125MBIT 32KX36 3.5NS 100TQFP - Bulk |
| CY7C1219F-133AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C12235DC | 制造商:CYPRESS 功能描述:New |
發布緊急采購，3分鐘左右您將得到回復。