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參數(shù)資料
| 型號(hào)： | CY7C1327F-133BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mb (256K x 18) Pipelined Sync SRAM |
| 中文描述： | 256K X 18 CACHE SRAM, 4 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁(yè)數(shù)： | 1/17頁(yè) |
| 文件大小： | 572K |
| 代理商： | CY7C1327F-133BGI |
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4-Mb (256K x 18) Pipelined Sync SRAM
CY7C1327F
Cypress Semiconductor Corporation
Document #: 38-05216 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised December 12, 2003
Features
Registered inputs and outputs for pipelined operation
256K ×18 common I/O architecture
3.3V core power supply
3.3V / 2.5V I/O operation
Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Offered in JEDEC-standard 100-pin TQFP and 119 Ball
BGA packages.
“ZZ” Sleep Mode Option
Logic Block Diagram
Functional Description
[1]
The CY7C1327F SRAM integrates 262,144 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE
2
and
CE
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1327F operates from a +3.3V core power supply
while all outputs also operate with a +3.3V or a +2.5V supply.
All
inputs
and
outputs
JESD8-5-compatible.
are
JEDEC-standard
1
Note:
1. For best–practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com
A0, A1, A
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC
BW
B
BW
A
BWE
CE
1
CE2
CE3
DQ
B,
DQP
B
WRITE REGISTER
DQ
A,
DQP
A
WRITE REGISTER
ENABLE
REGISTER
OE
SENSE
ARRAY
ADSP
2
MODE
GW
PIPELINED
ENABLE
DQs
DQP
A
DQP
B
OUTPUT
REGISTERS
INPUT
REGISTERS
E
DQ
A,
DQP
A
WRITE DRIVER
OUTPUT
BUFFERS
DQ
B,
DQP
B
WRITE DRIVER
A[1:0]
ZZ
SLEEP
CONTROL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1327F-166AC | 4-Mb (256K x 18) Pipelined Sync SRAM |
| CY7C1327F-166AI | 4-Mb (256K x 18) Pipelined Sync SRAM |
| CY7C1327F-166BGC | 4-Mb (256K x 18) Pipelined Sync SRAM |
| CY7C1327F-166BGI | 4-Mb (256K x 18) Pipelined Sync SRAM |
| CY7C1327F-200AC | 4-Mb (256K x 18) Pipelined Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1327G-100AXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 3.3V IND Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1327G-100AXIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 3.3V IND Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1327G-100BGXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1327G-100BGXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1327G-133AXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 3.3V IND Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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