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參數(shù)資料
| 型號(hào)： | CY7C1339F-166BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (128K x 32) Pipelined Sync SRAM |
| 中文描述： | 128K X 32 CACHE SRAM, 3.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 418K |
| 代理商： | CY7C1339F-166BGC |
4-Mbit (128K x 32) Pipelined Sync SRAM
CY7C1339F
Cypress Semiconductor Corporation
Document #: 38-05217 Rev. *C
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 09, 2004
Features
Registered inputs and outputs for pipelined operation
128K × 32 common I/O architecture
3.3V core power supply
2.5V / 3.3V I/O operation
Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Offered in JEDEC-standard 100-pin TQFP and 119-ball
BGA packages
“ZZ” Sleep Mode Option
Logic Block Diagram
Functional Description
[1]
The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE
2
and
CE
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1339F operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
1
Note:
1. For best–practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER
AND
LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
SENSE
OUTPUT
BUFFERS
E
PIPELINED
ENABLE
INPUT
REGISTERS
A0, A1, A
BW
B
BW
C
BW
D
BW
A
MEMORY
ARRAY
DQ s
SLEEP
CONTROL
ZZ
A
[1:0]
2
DQ
A
BYTE
WRITE REGISTER
DQ
B
BYTE
WRITE REGISTER
DQ
C
BYTE
WRITE REGISTER
DQ
D
BYTE
WRITE REGISTER
DQ
A
BYTE
WRITE DRIVER
DQ
B
BYTE
WRITE DRIVER
DQ
C
BYTE
WRITE DRIVER
DQ
D
BYTE
WRITE DRIVER
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1339F-166BGI | DIODE ZENER SINGLE 350mW 3.9Vz 20mA-Izt 0.05 10uA-Ir 1 SOT-23 3K/REEL |
| CY7C1339F-200AC | 4-Mbit (128K x 32) Pipelined Sync SRAM |
| CY7C1339F-200AI | DIODE ZENER DUAL ISOLATED 200mW 3.9Vz 20mA-Izt 0.05 10uA-Ir 1 SOT-363 3K/REEL |
| CY7C1339F-200BGC | DIODE ZENER SINGLE 150mW 3.9Vz 20mA-Izt 0.05 10uA-Ir 1 SOT-523 3K/REEL |
| CY7C1339F-200BGI | DIODE ZENER TRIPLE ISOLATED 200mW 3.9Vz 20mA-Izt 0.05 10uA-Ir 1 SOT-363 3K/REEL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1339G-100AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 128Kx32 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1339G-100AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 128Kx32 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1339G-100BGI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 128Kx32 3.3V IND Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1339G-100BGIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 128Kx32 3.3V IND Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1339G-100BGXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 128Kx32 3.3V IND Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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