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參數資料
| 型號： | CY7C1342-55JI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores |
| 中文描述： | 4K X 8 DUAL-PORT SRAM, 55 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 506K |
| 代理商： | CY7C1342-55JI |
4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port
SRAM with Semaphores
CY7C135
CY7C1342
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-06038 Rev. *B
Revised June 22, 2004
Features
True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
4K x 8 organization
0.65-micron CMOS for optimum speed/power
High-speed access: 15 ns
Low operating power: I
CC
= 160 mA (max.)
Fully asynchronous operation
Automatic power-down
Semaphores included on the 7C1342 to permit software
handshaking between ports
Available in 52-pin PLCC
Functional Description
The CY7C135 and CY7C1342 are high-speed CMOS 4K x 8
dual-port static RAMs. The CY7C1342 includes semaphores
that provide a means to allocate portions of the dual-port RAM
or any shared resource. Two ports are provided permitting in-
dependent, asynchronous access for reads and writes to any
location in memory. Application areas include interproces-
sor/multiprocessor designs, communications status buffering,
and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). The
CY7C135 is suited for those systems that do not require
on-chip arbitration or are intolerant of wait states. Therefore,
the user must be aware that simultaneous access to a location
is possible. Semaphores are offered on the CY7C1342 to as-
sist in arbitrating between ports. The semaphore logic is com-
prised of eight shared latches. Only one side can control the
latch (semaphore) at any time. Control of a semaphore indi-
cates that a shared resource is in use. An automatic pow-
er-down feature is controlled independently on each port by a
chip enable (CE) pin or SEM pin (CY7C1342 only).
The CY7C135 and CY7C1342 are available in 52-pin PLCC.
1342–1
R/W
L
CE
L
OE
L
A
11L
A
0L
A
0R
A
11R
R/W
R
CE
R
OE
R
CE
R
OE
R
CE
L
OE
L
R/W
L
R/W
R
I/O
7L
I/O
0L
I/O
7R
I/O
0R
SEMAPHORE
ARBITRATION
(7C1342 only)
CONTROL
I/O
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
(7C1342 only)
SEM
L
SEM
R
Logic Block Diagram
(7C1342 only)
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