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參數(shù)資料
| 型號： | CY7C1345G-133BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (128K x 36) Flow-Through Sync SRAM |
| 中文描述： | 128K X 36 CACHE SRAM, 6.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大小： | 331K |
| 代理商： | CY7C1345G-133BGXC |
PRELIMINARY
4-Mbit (128K x 36) Flow-Through Sync SRAM
CY7C1345G
Cypress Semiconductor Corporation
Document #: 38-05517 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised October 21, 2004
Features
128K X 36 common I/O
3.3V –5% and +10% core power supply (V
DD
)
2.5V or 3.3V I/O supply (V
DDQ
)
Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
— 8.0 ns (100-MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Lead-Free 100-pin TQFP and 119-ball BGA packages
“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1345G is a 131,072 x 36 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE
2
and
CE
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW
x
,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
The CY7C1345G allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1345G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Note:
1. For best–practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
CLR
Q1
Q0
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
MEMORY
ARRAY
MODE
A
[1:0]
ZZ
DQs
DQP
A
DQP
B
DQP
C
DQP
D
A0, A1, A
ADV
CLK
ADSP
ADSC
BW
D
BW
C
BW
B
BW
A
BWE
CE1
CE2
CE3
OE
GW
SLEEP
CONTROL
DQ
A
,
DQP
A
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
BYTE
WRITE REGISTER
BYTE
WRITE REGISTER
DQ
D
,
DQP
D
DQ
D
,
DQP
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BYTE
WRITE REGISTER
DQ
A
,
DQP
A
BYTE
WRITE REGISTER
Logic Block Diagram
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PDF描述 |
|---|---|
| CY7C1345G-133BGXI | 4-Mbit (128K x 36) Flow-Through Sync SRAM |
| CY7C1345 | 128K x 36 Synchronous Flow-Through 3.3V Cache RAM(3.3V 128K x 36 同步流通式高速緩沖RAM) |
| CY7C1346H | 2-Mbit (64K x 36) Pipelined Sync SRAM |
| CY7C1346H-166AXC | 2-Mbit (64K x 36) Pipelined Sync SRAM |
| CY7C1346H-166AXI | 2-Mbit (64K x 36) Pipelined Sync SRAM |
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