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參數資料
| 型號： | CY7C1347B-100AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 128K x 36 Synchronous-Pipelined Cache RAM |
| 中文描述： | 128K X 36 CACHE SRAM, 5.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 566K |
| 代理商： | CY7C1347B-100AC |
128K x 36 Synchronous-Pipelined Cache RAM
CY7C1347B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
March 11, 2001
1CY7C1347
Features
Supports 100-MHz bus for Pentium
and PowerPC
operations with zero wait states
Fully registered inputs and outputs for pipelined oper-
ation
128K by 36 common I/O architecture
3.3V core power supply
2.5V/3.3V I/O operation
Fast clock-to-output times
—3.5 ns (for 166-MHz device)
—4.0 ns (for 133-MHz device)
—5.5 ns (for 100-MHz device)
User-selectable burst counter supporting Intel
tium interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100 TQFP pinout
“ZZ” Sleep Mode option and Stop Clock option
Available in Industrial and Commercial Temperature
ranges
Pen-
Functional Description
The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined
cache SRAM designed to support zero-wait-state secondary
cache with minimal glue logic.
Logic Block Diagram
The CY7C1347B I/O pins can operate at either the 2.5V or the
3.3V level, the I/O pins are 3.3V tolerant when V
DDQ
= 2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1347B supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The burst
sequence is selected through the MODE pin. Accesses can be
initiated by asserting either the Processor Address Strobe
(ADSP) or the Controller Address Strobe (ADSC) at clock rise.
Address advancement through the burst sequence is con-
trolled by the ADV input. A 2-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
Byte write operations are qualified with the four Byte Write
Select (BW
[3:0]
) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
Pentium and Intel are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
CLK
ADV
ADSC
ADSP
A
[16:0]
GW
BWE
BW
3
BW
2
BW
1
BW
0
1
CE
2
CE
3
OE
ZZ
BURST
COUNTER
ADDRESS
REGISTER
ROUTPUT
CLK
RINPUT
CLK
128KX36
MEMORY
ARRAY
Q
0
Q
1
Q
D
CE
CLR
SLEEP
CONTROL
36
36
17
15
15
17
(A
[1;0]
)
2
MODE
DQ
[31:0]
DP
[3:0]
DQ[31:24], DP[3]
REGISTERS
DQ[23:16], DP[2]
BYTEWRITE
REGISTERS
BYTEWRITE
REGISTERS
DQ[7:0], DP[0]
BYTEWRITE
REGISTERS
D
Q
D
Q
D
Q
D
Q
ENABLE CE
REGISTER
D
Q
ENABLE DELAY
REGISTER
D
Q
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| CY7C1347B-100ACT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Cypress Semiconductor 功能描述: |
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| CY7C1347B-133BGCT | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
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