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參數資料
| 型號： | CY7C1350B-133AI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 128Kx36 Pipelined SRAM with NoBL Architecture |
| 中文描述： | 128K X 36 ZBT SRAM, 4.2 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 210K |
| 代理商： | CY7C1350B-133AI |
PRELIMINARY
128Kx36 Pipelined SRAM with NoBL Architecture
Functional Description
CY7C1350B
Cypress Semiconductor Corporation
Document #: 38-05045 Rev. **
3901 North First Street
San Jose
CA 95134
Revised September 7, 2001
408-943-2600
350B
Features
Pin compatible and functionally equivalent to ZBT
devices IDT71V546, MT55L128L36P, and MCM63Z736
Supports 166-MHz bus operations with zero wait states
—Data is transferred on every clock
Internally self-timed output buffer control to eliminate
the need to use OE
Fully registered (inputs and outputs) for pipelined
operation
Byte Write capability
128K x 36 common I/O architecture
Single 3.3V power supply
Fast clock-to-output times
—3.5 ns (for 166-MHz device)
—3.8 ns (for 150-MHz device)
—4.0 ns (for 143-MHz device)
—4.2 ns (for 133-MHz device)
—5.0 ns (for 100-MHz device)
—7.0 ns (for 80-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100 TQFP package
Burst Capability—linear or interleaved burst order
Low standby power (17.325 mW max.)
Logic Block Diagram
The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1350B is equipped with the advanced
No Bus Latency
(NoBL
) logic required to enable consec-
utive Read/Write operations with data being transferred on ev-
ery clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions. The CY7C1350B is pin/func-
tionally
compatible
to
ZBT
MT55L128L36P, and MCM63Z736.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
3.5 ns (166-MHz device).
Write operations are controlled by the four Byte Write Select
(BWS
[3:0]
) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
SRAMs
IDT71V546,
.
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
CLK
A
[16:0]
CEN
CE1
CE2
WE
BWS
[3:0]
MODE
CE
OE
O
128Kx36
MEMORY
ARRAY
C
DQ
[31:0]
DP
[3:0]
DaD
Q
36
CE
CONTROL
and WRITE
LOGIC
3
R
a
ADV/LD
36
36
36
17
17
Selection Guide
-166
3.5
400
5
-150
3.8
375
5
-143
4.0
350
5
-133
4.2
300
5
-100
5.0
250
5
-80
7.0
200
5
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Commercial
Commercial
Shaded areas contain advance information.
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| CY7C1350B-143AC | 128Kx36 Pipelined SRAM with NoBL Architecture |
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| CY7C1350B-166AC | 128Kx36 Pipelined SRAM with NoBL Architecture |
| CY7C1350G-100AXC | 4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C1350F-133AI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1350F-200AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 2.8ns 100-Pin TQFP |
| CY7C1350F-200ACT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 2.8ns 100-Pin TQFP T/R |
| CY7C1350F-250AXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1350G-100AXC | 制造商:MAJOR 功能描述: |
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