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參數資料
| 型號： | CY7C1350G-200BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture |
| 中文描述： | 128K X 36 ZBT SRAM, 2.8 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁數： | 1/15頁 |
| 文件大小： | 298K |
| 代理商： | CY7C1350G-200BGI |
PRELIMINARY
4-Mbit (128K x 36) Pipelined SRAM
with NoBL Architecture
CY7C1350G
Cypress Semiconductor Corporation
Document #: 38-05524 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised October 14, 2004
Features
Pin compatible and functionally equivalent to ZBT
devices
Internally self-timed output buffer control to eliminate
the need to use OE
Byte Write capability
128K x 36 common I/O architecture
Single 3.3V power supply
2.5V/3.3V I/O Operation
Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable (OE)
Lead-Free 100 TQFP and 119 BGA packages
Burst Capability—linear or interleaved burst order
“ZZ” Sleep mode option
Logic Block Diagram
Functional Description
[1]
The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1350G is equipped with the advanced
No Bus Latency (NoBL) logic required to enable consec-
utive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.6 ns (250-MHz device)
Write operations are controlled by the four Byte Write Select
(BW
[A:D]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
A0, A1, A
C
MODE
BW
A
B
BW
C
D
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
A
DQP
B
DQP
C
DQP
D
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
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