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參數資料
| 型號： | CY7C1351 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mb (128K x 36) Flow-through SRAM with NoBL⑩ Architecture |
| 中文描述： | 4字節（128K的× 36）流通過總線延遲⑩建筑的SRAM |
| 文件頁數： | 1/15頁 |
| 文件大小： | 427K |
| 代理商： | CY7C1351 |
4-Mb (128K x 36) Flow-through SRAM with
NoBL Architecture
CY7C1351F
Cypress Semiconductor Corporation
Document #: 38-05210 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 12, 2004
Features
Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT
devices
Internally self-timed output buffer control to eliminate
the need to use OE
Registered inputs for flow-through operation
Byte Write capability
128K x 36 common I/O architecture
2.5V / 3.3V I/O power supply
Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
— 8.0 ns (for 100-MHz device)
— 11.0 ns (for 66-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous Output Enable
JEDEC-standard 100 TQFP and 119 BGA packages
Burst Capability—linear or interleaved burst order
Low standby power
Functional Description
[1]
The CY7C1351F is a 3.3V, 128K x 36 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1351F is equipped with the
advanced No Bus Latency (NoBL) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the four Byte Write Select
(BW
[A:D]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
1
Note:
1. For best–practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Logic Block Diagram
C
MODE
BW
A
BW
B
WE
CE1
CE2
CE3
OE
READ
LOGIC
DQs
DQP
A
DQP
B
DQP
C
DQP
D
MEMORY
ARRAY
E
INPUT
REGISTER
BW
C
BW
D
ADDRESS
REGISTER
WRITE
REGISTRY
AND
DATA
COHERENCY
CONTROL
LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
ADV/LD
CE
ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
S
E
ZZ
SLEEP
Control
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1351F-117BGI | 4-Mb (128K x 36) Flow-through SRAM with NoBL⑩ Architecture |
| CY7C1351F-133AC | 4-Mb (128K x 36) Flow-through SRAM with NoBL⑩ Architecture |
| CY7C1351F-133AI | 4-Mb (128K x 36) Flow-through SRAM with NoBL⑩ Architecture |
| CY7C1351F-133BGC | 4-Mb (128K x 36) Flow-through SRAM with NoBL⑩ Architecture |
| CY7C1351F-133BGI | 4-Mb (128K x 36) Flow-through SRAM with NoBL⑩ Architecture |
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