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參數(shù)資料
| 型號(hào)： | CY7C1353-40AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256Kx18 Flow-Through SRAM with NoBL Architecture |
| 中文描述： | 256K X 18 ZBT SRAM, 14 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 172K |
| 代理商： | CY7C1353-40AC |
256Kx18 Flow-Through SRAM with NoBL Architecture
Functional Description
CY7C1353
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
March 3, 1999
1353
Features
Pin compatible and functionally equivalent to ZBT
devices MCM63Z819 and MT55L256L18F
Supports 66-MHz bus operations with zero wait states
—Data is transferred on every clock
Internally self-timed output buffer control to eliminate
the need to use OE
Registered inputs for Flow-Through operation
Byte Write capability
256K x 18 common I/O architecture
Single 3.3V power supply
Fast clock-to-output times
—11.0 ns (for 66-MHz device)
—12. 0 ns (for 50-MHz device)
—14.0 ns (for 40-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous Output Enable
JEDEC-standard 100 TQFP package
Burst Capability—linear or interleaved burst order
Low standby power
The CY7C1353 is a 3.3V 256K by 18 Synchronous-
Flow-Through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353 is equipped with the
advanced No Bus Latency (NoBL
) logic required to enable
consecutive Read/Write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems
that require frequent Write-Read transitions.The CY7C1353 is
pin/functionally compatible to ZBT
SRAMs MCM63Z819 and
MT55L256L18F.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 9.0 ns (66-MHz de-
vice).
Write operations are controlled by the four Byte Write Select
(BWS
[1:0]
) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
CLK
A
[17:0]
CEN
CE1
CE2
WE
[1:0]
Mode
BWS
CE
OE
256KX18
MEMORY
ARRAY
Logic Block Diagram
DQ
[15:0]
DP
[1:0]
DD
Q
18
CE
CONTROL
and WRITE
LOGIC
3
ADV/LD
18
18
18
18
Selection Guide
7C1353-66
7C1353-50
7C1353-40
Maximum Access Time (ns)
11
12.0
14.0
Maximum Operating Current (mA)
Commercial
250 mA
200 mA
175 mA
Maximum CMOS Standby Current (mA)
Commercial
5 mA
5 mA
5 mA
NoBL is a trademark of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C135350AC | 制造商:CYPRESS 功能描述:* |
| CY7C1353B-66AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1353F-100AC | 功能描述:IC SRAM 4.5MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1353F-100ACT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 256K x 18 8ns 100-Pin TQFP T/R 制造商:Rochester Electronics LLC 功能描述:4M- 256KX18 3.3V FLOW-THROUGH-NOBL SRAM - Tape and Reel |
| CY7C1353G-100AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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