- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄380192 > CY7C1354A-100ACI (CYPRESS SEMICONDUCTOR CORP) 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C1354A-100ACI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture |
| 中文描述： | 256K X 36 ZBT SRAM, 5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 1/31頁(yè) |
| 文件大小： | 560K |
| 代理商： | CY7C1354A-100ACI |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)
256K x 36/512K x 18 Pipelined SRAM
with NoBL Architecture
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Cypress Semiconductor Corporation
Document #: 38-05161 Rev. *B
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised April 25, 2002
Features
Zero Bus Latency, no dead cycles between Write and
Read cycles
Fast clock speed: 200, 166, 133, 100 MHz
Fast access time: 3.2, 3.6, 4.2, 5.0 ns
Internally synchronized registered outputs eliminate
the need to control OE
Single 3.3V –5% and +5% power supply V
CC
Separate V
CCQ
for 3.3V or 2.5V I/O
Single WEN (Read/Write) control pin
Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
Interleaved or linear four-word burst capability
Individual byte Write (BWa–BWd) control (may be tied
LOW)
CEN pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Automatic power-down feature available using ZZ mode
or CE select
JTAG boundary scan
Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid
Array), and 100-pin TQFP packages
Functional Description
The
GVT71512ZC18 SRAMs are designed to eliminate dead
cycles when transitioning from Read to Write or vice versa.
These SRAMs are optimized for 100% bus utilization and
achieve Zero Bus Latency
(ZBL
)/No Bus Latency
(NoBL
). They integrate 262,144
×
36 and 524,288
×
18
SRAM cells, respectively, with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. These employ high-speed, low-power CMOS
designs using advanced triple-layer polysilicon, double-layer
metal technology. Each memory cell consists of four
transistors and two high-valued resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
CY7C1354A/GVT71256ZC36
and
CY7C1356A/
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE, CE
2
, and CE
3
), Cycle Start Input (ADV/LD),
Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,
and BWd), and Read-Write Control (WEN). BWc and BWd
apply to CY7C1354A/GVT71256ZC36 only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data
occurs, either Read or Write.
A clock enable (CEN) pin allows operation of the
CY7C1354A/GVT71256ZC36/CY7C1356A/GVT71512ZC18
to be suspended as long as necessary. All synchronous inputs
are ignored when (CEN) is HIGH and the internal device
registers will hold their previous values.
There are three chip enable pins (CE, CE
2
, CE
3
) that allow the
user to deselect the device when desired. If any one of these
three are not active when ADV/LD is LOW, no new memory
operation can be initiated and any burst cycle in progress is
stopped. However, any pending data transfers (Read or Write)
will be completed. The data bus will be in high-impedance
state two cycles after chip is deselected or a Write cycle is
initiated.
The
CY7C1354A/GVT71256ZC36
GVT71512ZC18 have an on-chip two-bit burst counter. In the
burst
mode,
the
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18 provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the MODE input pin. The MODE pin
selects between linear and interleaved burst sequence. The
ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH)
Output Enable (OE), Sleep Enable (ZZ) and burst sequence
select (MODE) are the asynchronous signals. OE can be used
to disable the outputs at any given time. ZZ may be tied to
LOW if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
and
CY7C1356A/
and
Selection Guide
7C1354A-200
71256ZC36-5
7C1356A-200
71512ZC18-5
3.2
560
30
7C1354A-166
71256ZC36-6
7C1356A-166
71512ZC18-6
3.6
480
30
7C1354A-133
71256ZC36-7.5
7C1356A-133
71512ZC18-7.5
4.2
410
30
7C1354A-100
71256ZC36-10
7C1356A-100
71512ZC18-10
5.0
350
30
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current Commercial
Commercial
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1354A-100BGCI | 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture |
| CY7C1354A-133ACI | 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture |
| CY7C1354A-133BGCI | 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture |
| CY7C1354A-166ACI | 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture |
| CY7C1354A-166BGCI | 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1354A-100BGI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 5ns 119-Pin BGA |
| CY7C1354A-133BGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1354A-133BGI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1354A-166AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 3.6ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1354A-166AI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 3.6ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。