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參數資料
| 型號： | CY7C1354BV25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 36/512K x 18 Pipelined SRAM with NoBL⑩ Architecture |
| 中文描述： | 256 × 36/512K × 18流水線的SRAM架構的總線延遲⑩ |
| 文件頁數： | 1/27頁 |
| 文件大小： | 518K |
| 代理商： | CY7C1354BV25 |
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256K x 36/512K x 18 Pipelined SRAM with
NoBL Architecture
CY7C1354BV25
CY7C1356BV25
Cypress Semiconductor Corporation
Document #: 38-05292 Rev. *E
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised August 10, 2004
Features
Pin-compatible and functionally equivalent to ZBT
Supports 225-MHz bus operations with zero wait states
— Available speed grades are 225, 200 and 166 MHz
Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
Fully registered (inputs and outputs) for pipelined
operation
Byte Write capability
Single 2.5V power supply
Fast clock-to-output times
— 2.8 ns (for 225-MHz device)
— 3.2ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in 100 TQFP, 119 BGA, and 165 fBGA packag-
es
IEEE 1149.1 JTAG Boundary Scan
Burst capability—linear or interleaved burst order
“ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x
36 and 512K x 18 Synchronous pipelined burst SRAMs with
No Bus Latency (NoBL
)
logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1354BV25 and
CY7C1356BV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1354BV25
and CY7C1356BV25 are pin compatible and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
a
–BW
d
for
CY7C1354BV25
CY7C1356BV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
and
BW
a
–BW
b
for
A0, A1, A
C
MODE
BW
a
BW
b
c
BW
d
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
DQP
c
DQP
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
Logic Block Diagram-CY7C1354BV25 (256K x 36)
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1354BV25-166 | 256K x 36/512K x 18 Pipelined SRAM with NoBL⑩ Architecture |
| CY7C1354BV25-200 | 256K x 36/512K x 18 Pipelined SRAM with NoBL⑩ Architecture |
| CY7C1354BV25-225 | 256K x 36/512K x 18 Pipelined SRAM with NoBL⑩ Architecture |
| CY7C1357C | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture(9-Mb (256K x 36/512K x 18)流通式SRAM（NoBL結構）) |
| CY7C1360B-200AC | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C1354BV25-166AC | 制造商:Rochester Electronics LLC 功能描述:8M- 256KX36 2.5V PIPELINE-NOBL SRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1354BV25-166AXC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1354BV25-166BZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1354BV25-200AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 2.5V 9M-Bit 256K x 36 3ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:8M- 256KX36 2.5V PIPELINE-NOBL SRAM - Bulk |
| CY7C1354C-166AXC | 功能描述:靜態隨機存取存儲器 256Kx36 3.3V NoBL Sync PL COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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