- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380198 > CY7C1371D-133BZC (CYPRESS SEMICONDUCTOR CORP) Pin header, Discrete wire IDC connection (for Bus line), Discrete wire connectors; HRS No: 541-0660-6 00; Connector Type: Wire; Contact Gender: Male; Termination Style: Crimping; Current Rating(Amps)(Max.): 3; Contact Mating Area Plating: Gold; Operating Temperature Range (degrees C): -30 to 85; General Description: In-line male contact PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C1371D-133BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | Pin header, Discrete wire IDC connection (for Bus line), Discrete wire connectors; HRS No: 541-0660-6 00; Connector Type: Wire; Contact Gender: Male; Termination Style: Crimping; Current Rating(Amps)(Max.): 3; Contact Mating Area Plating: Gold; Operating Temperature Range (degrees C): -30 to 85; General Description: In-line male contact |
| 中文描述： | 512K X 36 ZBT SRAM, 6.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165 |
| 文件頁(yè)數(shù)： | 1/30頁(yè) |
| 文件大小： | 447K |
| 代理商： | CY7C1371D-133BZC |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)
PRELIMINARY
18-Mbit (512K x 36/1M x 18) Flow-Through
SRAM with NoBL Architecture
CY7C1371D
CY7C1373D
Cypress Semiconductor Corporation
Document #: 38-05556 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised November 3, 2004
Features
No Bus Latency
(NoBL
) architecture eliminates
dead cycles between write and read cycles
Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
Pin-compatible and functionally equivalent to ZBT
devices
Internally self-timed output buffer control to eliminate
the need to use OE
Registered inputs for flow-through operation
Byte Write capability
3.3V/2.5V I/O power supply
Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 8.5 ns (for 100-MHz device)
Clock Enable (CEN) pin to enable clock and suspend
operation
Synchronous self-timed writes
Asynchronous Output Enable
Offered in JEDEC-standard lead-free 100 TQFP, 119-ball
BGA and 165-ball fBGA packages
Three chip enables for simple depth expansion
Automatic Power-down feature available using ZZ
mode or CE deselect
JTAG boundary scan for BGA and fBGA packages
Burst Capability—linear or interleaved burst order
Low standby power
Functional Description
[1]
The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x
18 Synchronous Flow-through Burst SRAM designed specifi-
cally to support unlimited true back-to-back Read/Write opera-
tions without the insertion of wait states. The CY7C1371D/
CY7C1373D is equipped with the advanced No Bus Latency
(NoBL) logic required to enable consecutive Read/Write
operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BW
X
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Selection Guide
133 MHz
6.5
210
70
100 MHz
8.5
175
70
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1373D-100BGXC | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
| CY7C1373D-100BZC | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
| CY7C1373D-100BZI | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
| CY7C1373D-100BZXC | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
| CY7C1373D-100BZXI | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1371DV33-133AXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18Mb (512Kx36) 靜態(tài)隨機(jī)存取存儲(chǔ)器 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1371DV33-133BZI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18Mb (512Kx36) 靜態(tài)隨機(jī)存取存儲(chǔ)器 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1371KV33-100AXI | 功能描述:IC SRAM 18MBIT 100MHZ 100TQFP 制造商:cypress semiconductor corp 系列:NoBL?? 包裝:托盤 零件狀態(tài):在售 存儲(chǔ)器類型:易失 存儲(chǔ)器格式:SRAM 技術(shù):SRAM - 同步 存儲(chǔ)容量:18Mb （512K x 36） 時(shí)鐘頻率:100MHz 寫周期時(shí)間 - 字，頁(yè):- 訪問時(shí)間:8.5ns 存儲(chǔ)器接口:并聯(lián) 電壓 - 電源:3.135 V ~ 3.6 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:100-LQFP 供應(yīng)商器件封裝:100-TQFP（14x20） 標(biāo)準(zhǔn)包裝:72 |
| CY7C1371S-133AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 CY7C1371S-133AXC RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1371S-133AXCKJ | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。