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參數資料
| 型號： | CY7C1371D |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture(18-Mb (512K x 36/1M x 18)流通式SRAM（NoBL結構）) |
| 中文描述： | 18兆位（為512k × 36/1M × 18）流體系結構，通過與總線延遲（18 MB的（為512k × 36/1M × 18）流通式的SRAM（總線延遲結構）的SRAM） |
| 文件頁數： | 1/28頁 |
| 文件大小： | 414K |
| 代理商： | CY7C1371D |
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18-Mbit (512K x 36/1M x 18)
Flow-Through SRAM with NoBL Architecture
CY7C1371D
CY7C1373D
Cypress Semiconductor Corporation
Document #: 38-05556 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 29, 2006
Features
No Bus Latency
(NoBL
) architecture eliminates
dead cycles between write and read cycles
Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
Pin-compatible and functionally equivalent to ZBT
devices
Internally self-timed output buffer control to eliminate
the need to use OE
Registered inputs for flow-through operation
Byte Write capability
3.3V/2.5V I/O power supply (V
DDQ
)
Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
Clock Enable (CEN) pin to enable clock and suspend
operation
Synchronous self-timed writes
Asynchronous Output Enable
Available in JEDEC-standard lead-free 100-pin TQFP,
lead-free and non-lead-free 119-Ball BGA and 165-Ball
FBGA package.
Three chip enables for simple depth expansion
Automatic Power-down feature available using ZZ
mode or CE deselect
IEEE 1149.1 JTAG-Compatible Boundary Scan
Burst Capability—linear or interleaved burst order
Low standby power
Functional Description
[1]
The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1M x 18
Synchronous Flow-through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
without
the
insertion
CY7C1371D/CY7C1373D is equipped with the advanced No
Bus Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BW
X
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
of
wait
states.
The
Selection Guide
133 MHz
6.5
210
70
100 MHz
8.5
175
70
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C1371D-100AXC | 功能描述:靜態隨機存取存儲器 512Kx36 3.3V NoBL Sync FT 靜態隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1371D-100AXC | 制造商:Cypress Semiconductor 功能描述:IC SRAM 18MBIT PARALLEL 8.5NS TQFP100 |
| CY7C1371D-100AXCT | 功能描述:靜態隨機存取存儲器 512Kx36 3.3V NoBL Sync FT 靜態隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1371D-100AXI | 功能描述:靜態隨機存取存儲器 512Kx36 3.3V NoBL Sync FT 靜態隨機存取存儲器 IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1371D-100AXIKJ | 制造商:Cypress Semiconductor 功能描述: |
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