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參數資料
| 型號： | CY7C1380D |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM(18-Mb (512K x 36/1M x 18)管道式SRAM) |
| 中文描述： | 18兆位（為512k × 36/1M × 18）流水線的SRAM（18 - MB的（為512k × 36/1M × 18）管道式的SRAM） |
| 文件頁數： | 1/30頁 |
| 文件大小： | 554K |
| 代理商： | CY7C1380D |
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18-Mbit (512K x 36/1M x 18)
Pipelined SRAM
CY7C1380D
CY7C1382D
Cypress Semiconductor Corporation
Document #: 38-05543 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 23, 2006
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
3.3V core power supply
2.5V/3.3V I/O power supply
Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single Cycle Chip Deselect
Available in JEDEC-standard lead-free 100-pin TQFP,
lead-free and non-lead-free 119-ball BGA and 165-ball
FBGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1380D/CY7C1382D SRAM integrates 524,288 x 36
and 1,048,576 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE
1
), depth-expansion Chip
Enables (CE
2
and CE
3[2]
), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BW
X
, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1380D/CY7C1382D operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
2.6
350
70
200 MHz
3.0
300
70
167 MHz
3.4
275
70
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Notes:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. CE
3
, CE
2
are for TQFP and 165 FBGA package only. 119 BGA is offered only in 1 Chip Enable.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C1380D-133AXC | 功能描述:靜態隨機存取存儲器 512Kx36 3.3V COM 1CD Sync PL 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1380D-133AXCT | 功能描述:靜態隨機存取存儲器 512Kx36 3.3V COM 1CD Sync PL 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1380D-167AXC | 功能描述:靜態隨機存取存儲器 512Kx36 3.3V COM 1CD Sync PL 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1380D-167AXC | 制造商:Cypress Semiconductor 功能描述:IC SRAM 18MBIT PARALLEL 3.4NS TQFP100 制造商:Cypress Semiconductor 功能描述:IC, SRAM, 18MBIT, PARALLEL 3.4NS TQFP100 |
| CY7C1380D-167AXCB | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
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