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參數(shù)資料
| 型號(hào)： | CY7C1382D-250BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM |
| 中文描述： | 1M X 18 CACHE SRAM, 2.6 ns, PBGA165 |
| 封裝： | 15 X 13 MM, 1.4 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 1/29頁 |
| 文件大小： | 469K |
| 代理商： | CY7C1382D-250BZXC |
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18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1380D
CY7C1382D
PRELIMINARY
Cypress Semiconductor Corporation
Document #: 38-05543 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised October 28, 2004
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200 and 167 MHz
Registered inputs and outputs for pipelined operation
3.3V core power supply
2.5V / 3.3V I/O operation
Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single Cycle Chip Deselect
Offered in JEDEC-standard lead-free 100-pin TQFP,
119-ball BGA and 165-Ball fBGA packages
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1380D/CY7C1382D SRAM integrates 524,288 x 36
and 1,048,576 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE
), depth-expansion Chip
Enables (CE
2
and
CE
3[2]
), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BW
, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1380D/CY7C1382D operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
2.6
350
70
200 MHz
3.0
300
70
167 MHz
3.4
275
70
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best–practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. CE
3
, CE
2
are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.
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