- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380203 > CY7C1399B-20VC (CYPRESS SEMICONDUCTOR CORP) 32K x 8 3.3V Static RAM PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C1399B-20VC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 32K x 8 3.3V Static RAM |
| 中文描述： | 32K X 8 CACHE SRAM, 20 ns, PDSO28 |
| 封裝： | 0.300 INCH, SOJ-28 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大小： | 151K |
| 代理商： | CY7C1399B-20VC |
32K x 8 3.3V Static RAM
CY7C1399B
Cypress Semiconductor Corporation
Document #: 38-05071 Rev. *C
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised June 19, 2001
C1399B
Features
Single 3.3V power supply
Ideal for low-voltage cache memory applications
High speed
—10/12/15 ns
Low active power
—216 mW (max.)
Low-power alpha immune 6T cell
Plastic SOJ and TSOP packaging
Functional Description
[1]
The CY7C1399B is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory ex-
pansion is provided by an active LOW Chip Enable (CE) and
active LOW Output Enable (OE) and three-state drivers. The
device has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs are
both LOW, data on the eight data input/output pins (I/O
0
through I/O
7
) is written into the memory location addressed by
the address present on the address pins (A
0
through A
14
).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399B is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
Note:
1.
For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
21
24
23
22
Top View
SOJ
25
28
27
26
GND
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
WE
A
4
A
3
A
2
A
1
OE
A
0
V
CC
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
5
CE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
32K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
A
1
Selection Guide
1399B-10
10
60
500
50
1399B-12
12
55
500
50
1399B-15
15
50
500
50
1399B-20
20
45
500
50
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (
μ
A)
L
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1399B-20VI | 32K x 8 3.3V Static RAM |
| CY7C1399B-20ZC | 32K x 8 3.3V Static RAM |
| CY7C1399B-20ZI | 32K x 8 3.3V Static RAM |
| CY7C1399BL-10VC | 32K x 8 3.3V Static RAM |
| CY7C1399BL-10ZC | 32K x 8 3.3V Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1399B-20VCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 256K-Bit 32K x 8 20ns 28-Pin SOJ T/R |
| CY7C1399B-20ZC | 制造商:Rochester Electronics LLC 功能描述:256K (32K X 8)- FAST ASYNCH SRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1399B-20ZCT | 制造商:Rochester Electronics LLC 功能描述:256K (32K X 8)- FAST ASYNCH SRAM - Bulk |
| CY7C1399BL-12ZC | 制造商:Rochester Electronics LLC 功能描述:256K (32K X 8)- FAST ASYNCH SRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1399BL-12ZCT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。