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參數資料
| 型號： | CY7C141-55NI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1K x 8 Dual-Port Static Ram |
| 中文描述： | 1K X 8 DUAL-PORT SRAM, 55 ns, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 306K |
| 代理商： | CY7C141-55NI |
1K x 8 Dual-Port Static Ram
fax id: 5200
CY7C130/CY7C131
CY7C140/CY7C141
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
May 1989 – Revised March 27, 1997
1CY7C140
Features
True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
1K x 8 organization
0.65-micron CMOS for optimum speed/power
High-speed access: 15 ns
Low operating power: I
CC
= 90 mA (max.)
Fully asynchronous operation
Automatic power-down
Master CY7C130/CY7C131 easily expands data bus
width to 16 or more bits using slave CY7C140/CY7C141
BUSY output flag on CY7C130/CY7C131; BUSY input
on CY7C140/CY7C141
INT flag for port-to-port communication
Available in 48-pin DIP (CY7C130/140), 52-pin PLCC and
52-pin TQFP
Pin-compatible and functionally equivalent to
IDT7130/IDT7140
Functional Description
The CY7C130/CY7C131/CY7C140 and CY7C141 are
high-speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/ CY7C131 can be utilized as either a
standalone 8-bit dual-port static RAM or as a master dual-port
RAM in conjunction with the CY7C140/CY7C141 slave du-
al-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). Two flags are
provided on each port, BUSY and INT. BUSY signals that the
port is trying to access the same location currently being ac-
cessed by the other port. INT is an interrupt flag indicating that
data has been placed in a unique location (3FF for the left port
and 3FE for the right port). An automatic power-down feature
is controlled independently on each port by the chip enable
(CE) pins.
The CY7C130 and CY7C140 are available in 48-pin DIP. The
CY7C131 and CY7C141 are available in 52-pin PLCC and
PQFP.
s
Notes:
1.
CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor
CY7C140/CY7C141 (Slave): BUSY is input.
Open drain outputs: pull-up resistor required
2.
Logic Block Diagram
Pin Configurations
C130-1
C130-2
13
14
15
16
17
18
19
20
21
22
23
24
26
25
27
28
32
31
30
29
33
36
35
34
GND
1
2
3
4
5
6
7
8
9
10
11
12
38
37
39
40
44
43
42
41
45
48
47
46
R/W
L
BUSY
L
INT
L
OE
L
CE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
CE
R
R/W
R
BUSY
R
INT
R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
V
CC
DIP
Top View
7C130
7C140
R/W
L
CE
L
BUSY
L
OE
L
A
9L
A
0L
A
0R
A
9R
R/W
R
CE
R
OE
R
CE
R
OE
R
R/W
R
CE
L
OE
L
R/W
L
I/O
7L
I/O
0L
I/O
7R
I/O
0R
BUSY
R
INT
L
INT
R
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
AND
INTERRUPT LOGIC
CONTROL
I/O
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
[1]
[2]
[2]
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