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參數(shù)資料
| 型號： | CY7C1444AV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM(36-Mb (1M x 36/2M x 18)管道式DCD同步SRAM) |
| 中文描述： | 36兆位（1米x 36/2Mx 18）流水線雙氰胺同步靜態(tài)存儲器（36字節(jié)（100萬x 36/2M × 18）管道式雙氰胺同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 1/26頁 |
| 文件大小： | 435K |
| 代理商： | CY7C1444AV33 |
36-Mbit (1M x 36/2Mx 18) Pipelined
DCD Sync SRAM
CY7C1444AV33
CY7C1445AV33
Cypress Semiconductor Corporation
Document #: 38-05352 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 22, 2006
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
Optimal for performance (Double-Cycle deselect)
Depth expansion without wait state
3.3V core power supply
2.5V/3.3V I/O power supply
Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
CY7C1444AV33, CY7C1445AV33 available in
JEDEC-standard lead-free 100-pin TQFP package and
lead-free and non-lead-free 165-ball FBGA package
IEEE 1149.1 JTAG-compatible Boundary Scan
“ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1444AV33/CY7C1445AV33 SRAM integrates 1M x
36/2M x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE
1
), depth- expansion Chip
Enables (CE
2
and CE
3
), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BW
X
, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte
Write operations (see Pin Descriptions and Truth Table for
further details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
The CY7C1444AV33/CY7C1445AV33 operates from a +3.3V
core power supply while all outputs operate with a +3.3V or a
+2.5V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
2.6
475
120
200 MHz
3.2
425
120
167 MHz
3.4
375
120
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1445AV33 | 36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM(36-Mb (1M x 36/2M x 18)管道式DCD同步SRAM) |
| CY7C1470V25 | 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture(72-Mb (2M x 36/4M x 18/1M x 72)管道式SRAM（NoBL結構）) |
| CY7C1470V33 | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture(72-Mb (2M x 36/4M x 18/1M x 72)管道式SRAM（NoBL結構）) |
| CY7C1480V33-167AXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1480V33-167BZI | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1444AV33-167AXC | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 3.3V Sync PL 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1444AV33-167AXCT | 功能描述:IC SRAM 36MBIT 167MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C1444AV33-250AXI | 制造商:Cypress Semiconductor 功能描述:SYNC - Trays 制造商:Cypress Semiconductor 功能描述:IC SRAM 36MBIT 250MHZ 100TQFP 制造商:Cypress Semiconductor 功能描述:Async Fast SRAMs |
| CY7C144-55AC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C144-55AXC | 功能描述:靜態(tài)隨機存取存儲器 5V 8Kx8 CMOS Dual Port 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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