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參數(shù)資料
| 型號： | CY7C1512-15SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64K x 8 Static RAM |
| 中文描述： | 64K X 8 STANDARD SRAM, 15 ns, PDSO32 |
| 封裝： | 0.450 INCH, PLASTIC, SOIC-32 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 193K |
| 代理商： | CY7C1512-15SC |
PRELIMINARY
64K x 8 Static RAM
CY7C1512
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
June 1996 – Revised October 1996
408-943-2600
1CY7C1512
Features
High speed
—t
AA
= 15 ns
CMOS for optimum speed/power
Low active power
—770 mW
Low standby power
—28 mW
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and OE options
Functional Description
The CY7C1512 is a high-performance CMOS static RAM or-
ganized as 65,536 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
1
), an active
HIGH chip enable (CE
2
), an active LOW output enable (OE),
and three-state drivers. This device has an automatic pow-
er-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking chip enable
one (CE
1
) and write enable (WE) inputs LOW and chip enable
two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
15
).
Reading from the device is accomplished by taking chip en-
able one (CE
1
) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C1512 is available in standard TSOP type I and
450-mil-wide plastic SOIC packages.
Logic BlockDiagram
Pin Configurations
SOIC
A
1
A
2
A
3
A
4
A
5
A
6
A
7
COLUMN
DECODER
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
2
I/O
1
I/O
2
I/O
3
64K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
CE
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
19
18
20
24
23
22
21
25
28
27
26
Top View
29
32
31
30
16
17
GND
NC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
WE
A
13
A
8
A
9
A
11
V
CC
A
15
CE
2
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
1512-1
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A
10
1512-2
A
6
A
5
A
7
A
14
A
12
WE
CE
2
A
15
V
NC
NC
A
4
A
13
A
8
A
9
OE
A
10
(not to scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
I/O
2
I/O
1
I/O
0
A
0
GND
I/O
7
I/O
6
I/O
4
I/O
3
I/O
5
CE
1
A
11
17
A
1
A
2
A
3
TSOP I
Top View
Selection Guide
7C1512-15
15
140
7C1512-20
20
130
7C1512-25
25
120
7C1512-35
35
110
7C1512-70
70
110
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum CMOS
Standby Current (mA)
Commercial
Commercial
5
5
5
5
5
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