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參數資料
| 型號： | CY7C1527AV18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 72-Mbit DDR-II SRAM 2-Word Burst Architecture(2-Word脈沖結構，72-Mbit DDR-II SRAM) |
| 中文描述： | 72兆位的DDR - II SRAM的2字突發建筑（2字脈沖結構,72 -兆位的DDR - II SRAM的） |
| 文件頁數： | 1/30頁 |
| 文件大小： | 706K |
| 代理商： | CY7C1527AV18 |
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72-Mbit DDR-II SRAM 2-Word
Burst Architecture
CY7C1516AV18, CY7C1527AV18
CY7C1518AV18, CY7C1520AV18
Cypress Semiconductor Corporation
Document Number: 001-06982 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 27, 2007
Features
■
72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■
300 MHz clock for high bandwidth
■
2-word burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) at 300 MHz
■
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
■
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■
Synchronous internally self-timed writes
■
DDR-II operates with 1.5 cycle read latency when Delay Lock
Loop (DLL) is enabled
■
Operates as a DDR-I device with 1 cycle read latency in DLL
off mode
■
1.8V core power supply with HSTL inputs and outputs
■
Variable drive HSTL output buffers
■
Expanded HSTL output voltage (1.4V–V
DD
)
■
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1516AV18 – 8M x 8
CY7C1527AV18 – 8M x 9
CY7C1518AV18 – 4M x 18
CY7C1520AV18 – 2M x 36
Functional Description
The CY7C1516AV18, CY7C1527AV18, CY7C1518AV18, and
CY7C1520AV18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a 1-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with two 8-bit words in the case of CY7C1516AV18
and two 9-bit words in the case of CY7C1527AV18 that burst
sequentially into or out of the device. The burst counter always
starts with a “0” internally in the case of CY7C1516AV18 and
CY7C1527AV18. On CY7C1518AV18 and CY7C1520AV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1518AV18 and two 36-bit words in the case of
CY7C1520AV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
300 MHz
300
900
900
940
1080
278 MHz
278
860
860
860
985
250 MHz
250
800
800
800
900
200 MHz
200
700
700
700
735
167 MHz
167
650
650
650
650
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
x8
x9
x18
x36
相關PDF資料 |
PDF描述 |
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| CY7C167A-25PC | 16K x 1 Static RAM |
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| CY7C167A-35PC | 16K x 1 Static RAM |
| CY7C167A-35VC | 16K x 1 Static RAM |
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| CY7C1543KV18-400BZC | 功能描述:靜態隨機存取存儲器 72MB (4Mx18) 1.8v 400MHz QDR II 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1543KV18-400BZI | 功能描述:靜態隨機存取存儲器 72MB (4Mx18) 1.8v 400MHz QDR II 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1543KV18-450BZC | 功能描述:靜態隨機存取存儲器 4Mb x 18 450 MHz RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1543KV18-450BZI | 功能描述:靜態隨機存取存儲器 72MB (8Mx9) 1.8v 450MHz QDR II 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1543V18-333BZC | 功能描述:靜態隨機存取存儲器 72M Q2+ B4 (2.0) RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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