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參數(shù)資料
| 型號： | CY7C186-20ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 8Kx8 Static RAM |
| 中文描述： | 8K X 8 STANDARD SRAM, 20 ns, PDSO32 |
| 封裝： | 8 X 20 MM, TSOP1-32 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 157K |
| 代理商： | CY7C186-20ZC |
8Kx8 Static RAM
CY7C186
Cypress Semiconductor Corporation
Document #: 38-05280 Rev. **
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised March 22, 2002
86
Features
High speed
—20 ns
Low active power
—605 mW
Low standby power
—110 mW
CMOS for optimum speed/power
Easy memory expansion with CE
1
, CE
2
, and OE
features
TTL-compatible inputs and outputs
Automatic power-down when deselected
Functional Description
The CY7C186 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE
1
), an active HIGH
chip enable (CE
2
), and active LOW output enable (OE) and
three-state drivers. The device has an automatic power-down
feature (CE
1
), reducing the power consumption by over 80%
when deselected. The CY7C186 is in a 600-mil-wide PDIP
package and a 32-pin TSOP (std. pinout).
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE
1
and WE in-
puts are both LOW and CE
2
is HIGH, data on the eight data
input/output pins (I/O
0
through I/O
7
) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE
1
and OE
active LOW, CE
2
active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins are present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
LogicBlock Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
0
A
1
A
9
A
1
A
1
I/O
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
NC
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
GND
256 x 32 x 8
ARRAY
INPUT BUFFER
COLUMN DECODER
R
S
POWER
DOWN
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
1
CE
2
WE
OE
Top View
DIP
Selection Guide
[1]
7C186-20
20
110
20/15
7C186-25
25
100
20/15
7C186-35
35
100
20/15
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Notes:
1.
For military specifications, see the CY7C186A datasheet.
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| CY7C186-25 | 8Kx8 Static RAM |
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| CY7C186-35PC | 8Kx8 Static RAM |
| CY7C187A | 64K x 1 Static RAM(64Kx1 靜態(tài) RAM) |
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| CY7C18655PC | 制造商:Cypress Semiconductor 功能描述: |
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| CY7C186A-45DMB | 制造商:Cypress Semiconductor 功能描述: |
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