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參數資料
| 型號： | CY7C199-20ZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 32K x 8 Static RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 20 ns, PDSO28 |
| 封裝： | 8 X 13.40 MM, TSOP1-28 |
| 文件頁數： | 1/13頁 |
| 文件大小： | 317K |
| 代理商： | CY7C199-20ZI |
CY7C199
32K x 8 Static RAM
Cypress Semiconductor Corporation
Document #: 38-05160 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 7, 2003
Features
High speed
—10 ns
Fast t
DOE
CMOS for optimum speed/power
Low active power
—467 mW (max, 12 ns “L” version)
Low standby power
—0.275 mW (max, “L” version)
2V data retention (“L” version only)
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
Functional Description
The CY7C199 is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
Logic Block Diagram
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
0
through I/O
7
) is written into the memory location
addressed by the address present on the address pins (A
0
through A
14
). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
Pin Configurations
DIP / SOJ / SOIC
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
21
24
23
22
Top View
25
28
27
26
GND
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
WE
A
4
A
3
A
2
A
1
OE
A
0
V
CC
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
5
CE
1024 x 32 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
A
1
28
4
5
6
7
8
9
10
11
12
3 2 1
27
1314151617
26
25
24
23
22
21
20
19
18
A
VC
I
G
W
A
A
I
I
I
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
CE
I/O
7
I/O
6
A
3
A
2
A
1
OE
A
0
I/O
1
A
4
Top View
LCC
22
23
24
25
26
27
28
1
2
3
4
5
6
10
11
15
14
13
12
16
19
18
17
20
21
7
8
9
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
TSOP I
Top View
(not to scale)
Selection Guide
7C199
-8
8
120
7C199
-10
10
110
90
0.5
0.05
7C199
-12
12
160
90
10
0.05
7C199
-15
15
155
90
10
0.05
7C199
-20
20
150
90
10
0.05
7C199
-25
25
150
80
10
0.05
7C199
-35
35
140
70
10
0.05
7C199
-45
45
140
Unit
ns
mA
Maximum Access Time
Maximum Operating Current
L
Maximum CMOS Standby Current
0.5
10
mA
L
Shaded area contains advance information.
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