- 您現在的位置：買賣IC網 > PDF目錄298976 > CY7C2566KV18-450BZI (CYPRESS SEMICONDUCTOR CORP) 8M X 8 DDR SRAM, 0.37 ns, PBGA165 PDF資料下載
參數資料
| 型號： | CY7C2566KV18-450BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 8M X 8 DDR SRAM, 0.37 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數： | 1/28頁 |
| 文件大?。?/td> | 831K |
| 代理商： | CY7C2566KV18-450BZI |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
72-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.5 Cycle Read Latency) with ODT
PRELIMINARY
CY7C2566KV18, CY7C2577KV18
CY7C2568KV18, CY7C2570KV18
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 001-15889 Rev. *D
Revised April 24, 2009
Features
■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■ 550 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces
(data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ On-Die Termination (ODT) feature
Supported for D[x:0], BWS[x:0], and K/K inputs
■ Synchronous internally self-timed writes
■ DDR-II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR-I device with 1 cycle read latency
when DOFF is asserted LOW
■ Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD
[1]
Supports both 1.5V and 1.8V IO supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase Locked Loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C2566KV18 – 8M x 8
CY7C2577KV18 – 8M x 9
CY7C2568KV18 – 4M x 18
CY7C2570KV18 – 2M x 36
Functional Description
The CY7C2566KV18, CY7C2577KV18, CY7C2568KV18, and
CY7C2570KV18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of K and K. Each address location is associated with two 8-bit
words (CY7C2566KV18), 9-bit words (CY7C2577KV18), 18-bit
words (CY7C2568KV18), or 36-bit words (CY7C2570KV18) that
burst sequentially into or out of the device.
These devices have an On-Die Termination feature supported
for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate
external termination resistors, reduce cost, reduce board area,
and simplify board routing.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Table 1. Selection Guide
Description
550 MHz
500 MHz
450 MHz
400 MHz
Unit
Maximum Operating Frequency
550
500
450
400
MHz
Maximum Operating Current
x8
740
690
630
580
mA
x9
740
690
630
580
x18
760
700
650
590
x36
970
890
820
750
Note
1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD.
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C293AL-35WC | 2K X 8 UVPROM, 35 ns, CDIP24 |
| CY7C474-15DI | 32K X 9 OTHER FIFO, 15 ns, CDIP28 |
| CY7C474-15PI | 32K X 9 OTHER FIFO, 15 ns, PDIP28 |
| CZ12010T0050GBK | 0 MHz - 3000 MHz 50 ohm RF/MICROWAVE TERMINATION |
| CZ5360D | 25 V, 5 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-201AD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C25682KV18-400BZC | 功能描述:靜態隨機存取存儲器 72MB (4Mx18) 1.8v 400MHz DDR II 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C25682KV18-400BZXC | 功能描述:靜態隨機存取存儲器 72MB (4Mx18) 1.8v 400MHz DDR II 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C25682KV18-450BZC | 功能描述:靜態隨機存取存儲器 72MB (4Mx18) 1.8v 450MHz DDR II 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C25682KV18-500BZC | 功能描述:靜態隨機存取存儲器 72MB (4Mx18) 1.8v 500MHz DDR II 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C25682KV18-550BZXC | 功能描述:靜態隨機存取存儲器 72MB (4Mx18) 2.9v 550MHz DDR II 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發布緊急采購，3分鐘左右您將得到回復。