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參數(shù)資料
| 型號： | CY7C274-35QMB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 32K x 8 Power Switched and Reprogrammable PROM |
| 中文描述： | 32K X 8 UVPROM, 35 ns, CQCC32 |
| 封裝： | WINDOWED, LCC-32 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 237K |
| 代理商： | CY7C274-35QMB |
32K x 8 Power Switched and
Reprogrammable PROM
CY7C271
CY7C274
Cypress Semiconductor Corporation
Document #: 38-04008 Rev. *B
3901 North First Street
San Jose
CA 95134
Revised December 27, 2002
408-943-2600
1CY7C274
Features
CMOS for optimum speed/power
Windowed for reprogrammability
High speed
—30 ns (Commercial)
—35 ns (Military)
Low power
—660 mW (commercial)
—715 mW (military)
Super low standby power
—Less than 165 mW when deselected
EPROM technology 100% programmable
Slim 300-mil package (7C271)
Direct replacement for bipolar PROMs
Capable of withstanding >2001V static discharge
Functional Description
The CY7C271 and CY7C274 are high-performance
32,768-word by 8-bit CMOS PROMs. When disabled (CE
HIGH), the 7C271/7C274 automatically powers down into a
low-power stand-by mode. The CY7C271 is packaged in the
300-mil slim package. The CY7C274 is packaged in the
industry standard 600-mil package. Both the CY7C271 and
CY7C274 are available in a cerDIP package equipped with an
erasure window to provide for reprogrammability. When
exposed to UV light, the PROM is erased and can be repro-
grammed. The memory cells utilize proven EPROM floating
gate technology and byte-wide intelligent programming
algorithms.
The CY7C271 and CY7C274 offer the advantage of lower
power, superior performance, and programming yield. The
EPROM cell requires only 12.5V for the super voltage, and low
current requirements allow for gang programming. The
EPROM cells allow each memory location to be tested 100%
because each location is written into, erased, and repeatedly
exercised prior to encapsulation. Each PROM is also tested
for AC performance to guarantee that after customer
programming, the product will meet DC and AC specification
limits.
Reading the 7C271 is accomplished by placing active LOW
signals on CS
1
and CE, and an active HIGH on CS
2
. Reading the
7C274 is accomplished by placing active LOW signals on OE and
CE. The contents of the memory location addressed by the address
lines (A
0
A
14
) will become available on the output lines (O
0
O
7
).
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
17
18
19
20
24
23
22
21
25
28
27
26
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
V
CC
A
10
A
11
A
12
A
13
A
14
CS
1
CS
2
CE
O
7
O
6
O
5
O
4
O
3
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
POWER-DOWN
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
CE
256 x 1024
PROGRAMABLE
ARRAY
8 x 1 OF 128
12
13
31
4
5
6
7
8
9
10
11
3 2 1
30
14151617
26
25
24
23
22
21
VC
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
13
A
14
NC
O
7
O
6
O
G
A
12
A
A
O
O
181920
27
28
29
32
N
O
NC
O
0
A
13
(7C271) CS
1
(7C271) CS
2
(7C274) OE
A
9
A
A
A
CS
1
CS
2
CE
A
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
17
18
19
20
24
23
22
21
25
28
27
26
12
13
31
4
5
6
7
8
9
10
11
3 2 1
30
14151617
26
25
24
23
22
21
A
VC
A
181920
27
28
29
32
N
A
A
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
V
CC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
O
7
O
6
O
5
O
4
O
3
A
9
A
11
NC
OE
A
10
CE
O
7
O
6
A
8
V
PP
7C271
7C274
N
O
NC
O
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
VP
O
G
O
O
N
O
O
DIP/Flatpack
DIP/Flatpack
LCC/PLCC (Opaque Only)
7C271
7C274
X ADDRESS
Y ADDRESS
LCC/PLCC (Opaque Only)
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