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參數(shù)資料
| 型號(hào)： | CY7C373I |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | UltraLogic⑩ 64-Macrocell Flash CPLD |
| 中文描述： | UltraLogic⑩64宏單元CPLD的閃光 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 183K |
| 代理商： | CY7C373I |
UltraLogic 64-Macrocell Flash CPLD
CY7C373i
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Cypress Semiconductor Corporation
Document #: 38-03030 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 8, 2004
Features
64 macrocells in four logic blocks
64 I/O pins
5 dedicated inputs including 4 clock pins
In-System Reprogrammable (ISR) Flash
technology
— JTAG interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
— f
MAX
= 125 MHz
— t
PD
= 10 ns
— t
S
= 5.5 ns
— t
CO
= 6.5 ns
Fully PCI compliant
3.3V or 5.0V I/O operation
Available in 84-pin PLCC and 100-pin TQFP packages
Pin compatible with the CY7C374i
Functional Description
The CY7C373i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C373i is
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic F
LASH
370i devices, the CY7C373i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins.The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally,
because of the superior routability of the F
LASH
370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
Logic Block Diagram
PIM
INPUT
MACROCELL
CLOCK
INPUTS
INPUT
LOGIC
BLOCK
B
LOGIC
BLOCK
C
2
2
36
16
16
36
16 I/Os
16 I/Os
32
32
LOGIC
BLOCK
D
36
16
16
36
16 I/Os
16 I/Os
4
1
INPUT/CLOCK
MACROCELLS
I/O
0
-I/O
15
LOGIC
BLOCK
A
I/O
16
-I/O
31
I/O
48
I/O
63
I/O
32
I/O
47
Selection Guide
7C373i–125 7C373i–100
10
5.5
6.5
75
7C373i–83
15
8
8
75
7C373iL-83
15
8
8
45
7C373i–66
20
10
10
75
7C373iL–66
20
10
10
45
Maximum Propagation Delay
[1]
, t
PD
(ns)
Minimum Set-up, t
S
(ns)
Maximum Clock to Output
[1]
, t
CO
(ns)
Typical Supply Current, I
CC
(mA)
Note:
1. The 3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V.
12
6.0
6.5
75
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C373I-100AI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C373I-100JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 84-Pin PLCC |
| CY7C373I-125AC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 100-Pin TQFP |
| CY7C373I-66AC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells 5V 100-Pin TQFP |
| CY7C373I-66JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells 5V 84-Pin PLCC 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 84-Pin PLCC |
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