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參數資料
| 型號： | CY7C408A-15DMB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO |
| 中文描述： | 64 X 8 OTHER FIFO, 40 ns, CDIP28 |
| 封裝： | 0.300 INCH, CERDIP-28 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 344K |
| 代理商： | CY7C408A-15DMB |
64 x 8 Cascadable FIFO
64 x 9 Cascadable FIFO
CY7C408A
CY7C409A
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
July 1986 – Revised July 1994
408-943-2600
1CY7C409A
Features
64 x 8 and 64 x 9 first-in first-out (FIFO) buffer memory
35-MHz shift in and shift out rates
Almost Full/Almost Empty and Half Full flags
Dual-port RAM architecture
Fast (50-ns) bubble-through
Independent asynchronous inputs and outputs
Output enable (CY7C408A)
Expandable in word width and FIFO depth
5V
±
10% supply
TTL complete
Capable of withstanding greater than 2001V electro-
static discharge voltage
300-mil, 28-pin DIP
Functional Description
The CY7C408A and CY7C409A are 64-word deep by 8- or
9-bit wide first-in first-out (FIFO) buffer memories. In addition
to the industry-standard handshaking signals, almost full/al-
most empty (AFE) and half-full (HF) flags are provided.
AFE is HIGH when the FIFO is almost full or almost empty,
otherwise AFE is LOW. HF is HIGH when the FIFO is half full,
otherwise HF is LOW.
The CY7C408A has an output enable (OE) function.
The memory accepts 8- or 9-bit parallel words as its inputs (DI
0
– DI
8
) under the control of the shift in (SI) input when the input
ready (IR) control signal is HIGH. The data is output, in the
same order as it was stored on the DO
0
– DO
8
output pins
under the control of the shift out (SO) input when the output
ready (OR) control signal is HIGH. If the FIFO is full (IR LOW),
pulses at the SI input are ignored; if the FIFO is empty (OR
LOW), pulses at the SO input are ignored.
The IR and OR signals are also used to connect the FIFOs in
parallel to make a wider word or in series to make a deeper
buffer, or both.
Parallel expansion for wider words is implemented by logically
ANDing the IR an OR outputs (respectively) of the individual
FIFOs together (Figure 5). The AND operation insures that all
of the FIFOs are either ready to accept more data (IR HIGH)
or ready to output data (OR HIGH) and thus compensate for
variations in propagation delay times between devices.
Serial expansion (cascading) for deeper buffer memories is
accomplished by connecting data outputs of the FIFO closet
to the data source (upstream device) to the data inputs of the
following (downstream) FIFO (Figure 4). In addition, to insure
proper operation, the SO signal of the upstream FIFO must be
connected to the OR output of the upstream FIFO. In this serial
expansion configuration, the IR and OR signals are used to
pass data through the FIFOs.
Reading and writing operations are completely asynchronous,
allowing the FIFO to be used as a buffer between two digital
machines of widely differing operating frequencies. The high
shift in and shift out rates of these FIFOs, and their throughput
rate due to the fast bubblethrough time, which is due to their
dual-port RAM architecture, make them ideal for high-speed
communications and controllers.
Logic Block Diagram
Pin Configurations
C408A–1
INPUT
CONTROL
LOGIC
SI
IR
DATA IN
DI0
DI7
(7C409A)DI8
MASTER
RESET
MR
WRITEMULTIPLEXER
WRITE POINTER
READ MULTIPLEXER
READPOINTER
MEMORY
ARRAY
OUTPUT
CONTROL
LOGIC
DATAOUT
ALMOSTFULL/
ALMOSTEMPTY
HALF FULL
OE (7C408A)
D.
.
.
DO7
DO8(7C409A)
SO
OR
.
.
.
HF
AFE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
24
23
22
21
25
28
27
26
AFE
HF
IR
SI
DI0
DI1
GND
DI2
DI3
DI4
DI5
DI6
DI7
(7C408A) NC
(7C409A) DI8
VCC
MR
SO
OR
DO0
DO1
GND
DO2
DO3
DO4
DO5
DO6
DO7
OE (7C408A)
C408A–3
C408A–2
27
4
5
6
7
8
9
10
11
3 2 1
26
25
121314 15
22
21
20
19
1617 18
23
24
28
OR
DO0
DO1
GND
DO2
DO3
DO4
DI0
DI1
GND
DI2
DI3
DI4
DI5
7C408A
7C409A
7C408A
7C409A
Flag Definitions
HF
L
L
H
H
AFE
H
L
L
H
Words Stored
0 - 8
9 - 31
32 - 55
56 - 64
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C409A-25PC | 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO |
| CY7C409A-25VC | 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO |
| CY7C409A-35PC | 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO |
| CY7C409A-35VC | 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO |
| CY7C408A-25LMB | 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C408A-15PC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C408A-15VC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C408A25DC | 制造商:CYPRESS 功能描述:* |
| CY7C408A25PC | 制造商:CYPRESS 功能描述:* |
| CY7C408A-25PC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 64 x 8 28-Pin PDIP |
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