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參數(shù)資料
| 型號： | CY7C4211V-25AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs |
| 中文描述： | 512 X 9 OTHER FIFO, 15 ns, PQFP32 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 263K |
| 代理商： | CY7C4211V-25AC |
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Features
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Cypress Semiconductor Corporation
Document #: 38-06010 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised August 22, 2003
High-speed, low-power, first-in, first-out (FIFO)
memories
64 x 9 (CY7C4421V)
256 x 9 (CY7C4201V)
512 x 9 (CY7C4211V)
1K x 9 (CY7C4221V)
2K x 9 (CY7C4231V)
4K x 9 (CY7C4241V)
8K x 9 (CY7C4251V)
High-speed 66-MHz operation (15-ns read/write cycle
time)
Low power (I
CC
= 20 mA)
3.3V operation for low power consumption and easy
integration into low-voltage systems
5V-tolerant inputs V
IH max
= 5V
Fully asynchronous and simultaneous read and write
operation
Empty, Full, and Programmable Almost Empty and
Almost Full status flags
TTL compatible
Output Enable (OE) pin
Independent read and write enable pins
Center power and ground pins for reduced noise
Width expansion capability
Space saving 32-pin 7 mm × 7 mm TQFP
32-pin PLCC
Functional Description
The CY7C42X1V are high-speed, low-power, FIFO memories
with clocked read and write interfaces. All are nine bits wide.
Programmable features include Almost Full/Almost Empty
flags. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multi-
processor interfaces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a Free-Running Clock (WCLK) and two Write
Enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a Free-Running Read Clock (RCLK) and
two Read Enable Pins (REN1, REN2). In addition, the
CY7C42X1V has an Output Enable Pin (OE). The Read
(RCLK) and Write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 66 MHz are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
Logic Block Diagram
Pin Configuration
THREE-STATE
OUTPUTREGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D0
8
RCLK
EF
PAE
PAF
FF
Q0
8
WEN1
WCLK
RS
OE
D64 x 9
8Kx 9
WEN2/LD
REN1 REN2
PLCC
Top View
D
1
D
0
RCLK
REN2
V
CC
Q
8
Q
7
Q
6
Q
5
D
8
D
7
D
6
D
5
D
4
D
3
GND
REN1
WCLK
WEN2/LD
D
2
D
8
D
7
D
6
D
5
D
4
D
3
D
2
PAF
PAE
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
OE
4 3 2 1
3130
32
D
1
D
0
RCLK
REN2
GND
REN1
PAF
PAE
21
22
23
24
27
26
28
29
25
14151617181920
17
18
19
20
21
22
23
24
14 15 16
9 10 11 1213
31 30
32
2928 27
25
26
WEN1
RS
F
Q
0
Q
1
Q
2
Q
3
Q
4
E
F
Q
0
Q
1
Q
2
Q
3
Q
4
E
O
V
CC
Q
8
Q
7
Q
6
Q
5
WCLK
WEN2/LD
WEN1
R
TQFP
Top View
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4211V-25JC | Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs |
| CY7C4221V | Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs |
| CY7C4221V-15AC | Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs |
| CY7C4221V-15JC | Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs |
| CY7C4221V-25AC | Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C421-20AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C421-20JC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY7C421-20JCT | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 512 x 9 32-Pin PLCC T/R |
| CY7C421-20JXC | 功能描述:先進(jìn)先出 512x9 .300" PARALLEL CASCADEABLE 先進(jìn)先出 COM RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C421-20JXCT | 功能描述:先進(jìn)先出 512x9 .300" PARALLEL CASCADEABLE 先進(jìn)先出 COM RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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