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參數(shù)資料
| 型號(hào)： | CY7C4265-35 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8K/16K x 18 Deep Sync FIFOs |
| 中文描述： | 8K/16K × 18深同步FIFO的 |
| 文件頁(yè)數(shù)： | 1/22頁(yè) |
| 文件大小： | 348K |
| 代理商： | CY7C4265-35 |
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8K/16K x 18 Deep Sync FIFOs
CY7C4255
CY7C4265
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-06004 Rev. *B
Revised August 11, 2004
Features
High-speed, low-power, first-in first-out (FIFO)
memories
8K x 18 (CY7C4255)
16K x 18 (CY7C4265)
0.5 micron CMOS for optimum speed/power
High-speed 100-MHz operation (10-ns read/write cycle
times)
Low power — I
CC
= 45 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
TTL compatible
Retransmit function
Output Enable (OE
)
pins
Independent read and write enable pins
Center power and ground pins for reduced noise
Supports free-running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability
64-pin TQFP and 64-pin STQFP
Pin-compatible density upgrade to CY7C42X5 family
Pin-compatible density upgrade to
IDT72205/15/25/35/45
Functional Description
The CY7C4255/65 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can
be cascaded to increase FIFO depth. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and commu-
nications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a Free-Running Clock (WCLK) and a Write En-
able pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continu-
ally written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running Read Clock (RCLK) and a Read
Enable pin (REN). In addition, the CY7C4255/65 have an Output
Enable pin (OE). The read and write clocks may be tied together for
single-clock operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies up to 100
MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the Cascade Input (WXI,
RXI), Cascade Output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to V
SS
and the FL pin of all the remaining devic-
es should be tied to V
CC
.
Q
0 – 17
4255–1
THREE–STATE
OUTPUTREGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
EXPANSION
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D
0 – 17
REN
RCLK
FF
EF
PAE
PAF
SMODE
WEN
WCLK
RS
FL/RT
WXI
WXO/HF
OE
RAM
ARRAY
8K x 18
16K x 18
RXI
RXO
Logic Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4261-10AC | 16K/32K x 9 Deep Sync FIFOs |
| CY7C4261-15JI | 16K/32K x 9 Deep Sync FIFOs |
| CY7C4261-25AC | 16K/32K x 9 Deep Sync FIFOs |
| CY7C4261-25AI | 16K/32K x 9 Deep Sync FIFOs |
| CY7C4261-25JC | 16K/32K x 9 Deep Sync FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4265V-15ASC | 功能描述:IC FIFO 16KX18 SYNCHRONOUS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433 |
| CY7C4265V-15ASI | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 18 64-Pin TQFP |
| CY7C4271-10AI | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 9 32-Pin TQFP |
| CY7C4271-10JC | 功能描述:IC DEEP SYNC FIFO 32KX9 32-PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433 |
| CY7C4271-15AC | 功能描述:IC FIFO 32KX9 SYNCHRONOUS 32QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433 |
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