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參數資料
| 型號： | CY7C4265 |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | DRAM |
| 英文描述： | 8K/16Kx18 Deep Sync FIFOs |
| 中文描述： | 8K/16Kx18同步FIFO的深度 |
| 文件頁數： | 1/20頁 |
| 文件大小： | 422K |
| 代理商： | CY7C4265 |
8K/16Kx18 Deep Sync FIFOs
fax id: 5413
CY7C4255
CY7C4265
PRELIMINARY
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
July 1995 – Revised November 1996
408-943-2600
1CY7C4265
Features
High-speed, low-power, first-in first-out (FIFO)
memories
8K x 18 (CY7C4255)
16K x 18 (CY7C4265)
0.5 micron CMOS for optimum speed/power
High-speed 100-MHz operation (10 ns read/write cycle
times)
Low power — I
CC
=45 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
TTL compatible
Retransmit function
Output Enable (OE
)
pins
Independent read and write enable pins
Center power and ground pins for reduced noise
Supports free-running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability
64-pin PLCC and 64-pin TQFP
Pin-compatible density upgrade to CY7C42X5 family
Pin-compatible density upgrade to
IDT72205/15/25/35/45
Functional Description
The CY7C4255/65 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can
be cascaded to increase FIFO depth. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and commu-
nications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continu-
ally written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running read clock (RCLK) and a read
enable pin (REN). In addition, the CY7C4255/65 have an output
enable pin (OE). The read and write clocks may be tied together for
single-clock operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies up to 100
MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to V
SS
and the FL pin of all the remaining devic-
es should be tied to V
CC
.
Q
0 – 17
4255–1
THREE–STATE
OUTPUTREGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
EXPANSION
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D
0 – 17
REN
RCLK
FF
EF
PAE
PAF
SMODE
WEN
WCLK
RS
FL/RT
WXI
WXO/HF
OE
RAM
ARRAY
8K x 18
16K x 18
RXI
RXO
Logic Block Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C4255 | 8K/16Kx18 Deep Sync FIFOs |
| CY7C4271V | 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs |
| CY7C4271V-15JC | 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs |
| CY7C4271V-25JC | 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs |
| CY7C4275 | 32K/64Kx18 Deep Sync FIFOs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C4265-10AI | 制造商:Rochester Electronics LLC 功能描述: |
| CY7C4265-10AIKJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C4265-10ASXC | 功能描述:先進先出 16K X18 DEEP SYNC 先進先出 COM RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C4265-10AXI | 功能描述:先進先出 16K X18 DEEP SYNC 先進先出 IND RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C4265-15AC | 制造商:Rochester Electronics LLC 功能描述: |
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