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參數(shù)資料
| 型號： | CY7C439 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Bidirectional 2K x 9 FIFO( 2K x 9雙向 先進(jìn)先出) |
| 中文描述： | 雙向2K × 9的FIFO（2K × 9雙向先進(jìn)先出） |
| 文件頁數(shù)： | 1/17頁 |
| 文件大小： | 282K |
| 代理商： | CY7C439 |
Bidirectional 2K x 9 FIFO
CY7C439
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
October 1990 - Revised July 1994
408-943-2600
Features
2048 x 9 FIFO buffer memory
Bidirectional operation
High-speed 28.5-MHz asynchronous reads and writes
Simple control interface
Registered and transparent bypass modes
Flags indicate Empty, Full, and Half Full conditions
5V
±
10% supply
Available in 300-mil DIP, PLCC, LCC, and SOJ packages
TTL compatible
Functional Description
The CY7C439 is a 2048 x 9 FIFO memory capable of bidirec-
tional operation. As the term first-in first-out (FIFO) implies,
data becomes available to the output port in the same order
that it was presented to the input port. There are two pins that
indicate the amount of data contained within the FIFO
block—E/F (Empty/Full) and HF (Half Full). These pins can be
decoded to determine one of four states. Two 9-bit data ports
are provided. The direction selected for the FIFO determines
the input and output ports. The FIFO direction can be pro-
grammed by the user at any time through the use of the reset
pin (MR) and the bypass/direction pin (BYPA). There are no
control or status registers on the CY7C439, making the part
simple to use while meeting the needs of the majority of bidi-
rectional FIFO applications.
FIFO read and write operations may occur simultaneously, and
each can occur at up to 28.5 MHz. The port designated as the
write port drives its strobe pin (STBX, X = A or B) LOW to
initiate the write operation. The port designated as the read
port drives its strobe pin LOW to initiate the read operation.
Output port pins go to a high-impedance state when the asso-
ciated strobe pin is HIGH. All normal FIFO operations require
the bypass control pin (BYPX, X = A or B) to remain HIGH.
In addition to the FIFO, two other data paths are provided;
registered bypass and transparent bypass. Registered bypass
can be considered as a single-word FIFO in the reverse direc-
tion to the main FIFO. The
Logic Block Diagram
Pin Configurations
C439-1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
24
23
22
21
25
28
27
26
Top View
DIP
7C439
A
4
A
3
A
2
A
1
A
0
BYPA
GND
BYPB
BDA
B
0
B
1
B
2
B
3
B
4
A
5
A
6
A
7
A
8
E/F
STBA
V
CC
MR
STBB
HF
B
8
B
7
B
6
B
5
C439-2
C439-3
12
13
31
4
5
6
7
8
9
10
11
3 2 1
30
14 15 16 17
26
25
24
23
22
21
Top View
PLCC/LCC
1819 20
27
28
29
32
7C439
A
8
E/F
NC
STBA
V
CC
MR
STBB
HF
B
8
A
1
A
0
BYPA
GND
BYPB
BDA
B
0
NC
B
1
A
2
A
3
A
4
NCA
5
A
6
A
7
B
2
B
3
NC
B
4
B
5
B
6
B
7
PORTA
CONTROL
LOGIC
FLAG
CONTROL
TRANSPARENT
BYPASS
BYPASS
REGISTER
2048 x 9
FIFO
DIRECTION
CONTROL
RESET
&
DIRECTION
LOGIC
MR
PORTA
A
0
- A
8
PORTB
B
0
- B
8
STBB
BYPB
STBA
BYPA
E/F
HF
BDA
PORTB
CONTROL
LOGIC
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