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參數資料
| 型號： | CY7C68000-56PVCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 16-Bit Bidirectional Transceiver |
| 中文描述： | LINE TRANSCEIVER, PDSO56 |
| 封裝： | SSOP-56 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 237K |
| 代理商： | CY7C68000-56PVCT |
PRELIMINARY
TX2 USB 2.0 UTMI Transceiver
CY7C68000
Cypress Semiconductor Corporation
Document #: 38-08016 Rev. *E
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised November 2, 2004
1.0
EZ-USB
TX2
Features
The Cypress EZ-USB TX2
is a Universal Serial Bus (USB)
specification revision 2.0 transceiver, serial/deserializer, to a
parallel interface of either 16 bits at 30 MHz or eight bits at 60
MHz. The TX2 provides a high-speed physical layer interface
that operates at the maximum allowable USB 2.0 bandwidth.
This allows the system designer to keep the complex high-
speed analog USB components external to the digital ASIC
which decreases development time and associated risk. A
standard interface is provided that is USB 2.0-certified and is
compliant with Transceiver Macrocell Interface (UTMI) speci-
fication version 1.05 dated 3/29/01.
Two packages are defined for the family: 56-pin SSOP and 56-
pin QFN.
The function block diagram is shown in
Figure 1-1
.
UTMI-compliant/USB-2.0-certified for device operation
Operates in both USB 2.0 high speed (HS), 480
Mbits/second, and full speed (FS), 12 Mbits/second
Serial-to-parallel and parallel-to-serial conversions
8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirec-
tional external data interface
Synchronous field and EOP detection on receive pack-
ets
Synchronous field and EOP generation on transmit
packets
Data and clock recovery from the USB serial stream
Bit stuffing/unstuffing; bit stuff error detection
Staging register to manage data rate variation due to
bit stuffing/unstuffing
16-bit 30-MHz, and 8-bit 60-MHz parallel interface
Ability to switch between FS and HS terminations and
signaling
Supports detection of USB reset, suspend, and resume
Supports HS identification and detection as defined by
the USB 2.0 Specification
Supports transmission of resume signaling
3.3V operation
Two package options—56-pin QFN, and 56-pin SSOP
All required terminations, including 1.5K-ohm pull-up
on DPLUS, are internal to chip
Supports USB 2.0 test modes.
Figure 1-1. Block Diagram
USB
2.0
XCVR
Traffic
Sync
Elasticity
Buffer
Fast
Digital
Rx
Digital
Rx
Digital
Tx
Fast
Digital
Tx
Full-Speed Rx
Full-Speed Tx
High-Speed Tx
High-Speed Rx
BIDI Option
Also
OSC
20X
PLL
PLL_480
UTMI CLK
XTALIN/
OUT
USB
UTMI Rx Ctl
UTMI Tx Ctl
UTMI CLK
UTMI Rx Data 8/16
UTMI Rx Data 8/16
CY7C68000
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C68000-56PVXC | 功能描述:IC USB 2.0 TX2 TXRX 56-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發器 系列:CY7C 標準包裝:1,140 系列:AU 類型:收發器 驅動器/接收器數:1/1 規程:CAN 電源電壓:5.3 V ~ 27 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SO 包裝:管件 其它名稱:935267940512AU5790D14AU5790D14-ND |
| CY7C68000-56PVXCT | 功能描述:IC USB 2.0 TX2 TXRX 56-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發器 系列:CY7C 標準包裝:1,140 系列:AU 類型:收發器 驅動器/接收器數:1/1 規程:CAN 電源電壓:5.3 V ~ 27 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SO 包裝:管件 其它名稱:935267940512AU5790D14AU5790D14-ND |
| CY7C68000A56BAXC | 制造商:CYPRESS 功能描述:New |
| CY7C68000A-56BAXC | 功能描述:電信線路管理 IC MoBL USB TX2 RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CY7C68000A-56LFXC | 功能描述:電信線路管理 IC MoBL USB TX2 RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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