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參數資料
| 型號： | CY8C29X66 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | PSoC混合信號陣列 |
| 文件頁數： | 1/41頁 |
| 文件大小： | 622K |
| 代理商： | CY8C29X66 |
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June 2004
Cypress MicroSystems, Inc. 2004 — Document No. 38-12011 Rev. *F
1
PSoC Mixed Signal Array
Final Data Sheet
CY8C24123, CY8C24223, and CY8C24423
PSoC Functional Overview
The PSoC family consists of many
Mixed Signal Array with
On-Chip Controller
devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C24x23 family can have up to three IO
ports that connect to the global digital and analog interconnects,
providing access to 4 digital blocks and 6 analog blocks.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
Features
■
Powerful Harvard Architecture Processor
M8C Processor Speeds to 24 MHz
8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
3.0 to 5.25 V Operating Voltage
Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
Industrial Temperature Range: -40°C to +85°C
■
Advanced Peripherals (PSoC Blocks)
6 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 8-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART
- Multiple SPI
Masters or Slaves
- Connectable to all GPIO Pins
Complex Peripherals by Combining Blocks
■
Precision, Programmable Clocking
Internal ±2.5% 24/48 MHz Oscillator
High-Accuracy 24 MHz with Optional 32 kHz
Crystal and PLL
Optional External Oscillator, up to 24 MHz
Internal Oscillator for Watchdog and Sleep
■
Flexible On-Chip Memory
4K Bytes Flash Program Storage 50,000
Erase/Write Cycles
256 Bytes SRAM Data Storage
In-System Serial Programming (ISSP
)
Partial Flash Updates
Flexible Protection Modes
EEPROM Emulation in Flash
■
Programmable Pin Configurations
25 mA Sink on all GPIO
Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
Up to 10 Analog Inputs on GPIO
Two 30 mA Analog Outputs on GPIO
Configurable Interrupt on all GPIO
■
Additional System Resources
I
2
C
Slave, Master, and Multi-Master to
400 kHz
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
■
Complete Development Tools
Free Development Software
(PSoC Designer)
Full-Featured, In-Circuit Emulator and
Programmer
Full Speed Emulation
Complex Breakpoint Structure
128K Bytes Trace Memory
DIGITAL SYSTEM
SRAM
256 Bytes
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
CPU Core (M8C)
SROM
Flash 4K
Digital
Block Array
Multiply
Accum.
Switch
Mode
Pump
Internal
Voltage
Ref.
Digital
Clocks
POR and LVD
System Resets
Decimator
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref
Analog
Input
Muxing
I
2
C
(1 Rows,
4 Blocks)
Port 2
Port 1
Port 0Drivers
System Bus
Analog
Block
Array
(2 Columns,
6 Blocks)
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