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參數資料
| 型號： | CYC1021B-12VC |
| 英文描述： | IC-1MB CMOS SRAM |
| 中文描述： | 集成電路1MB的CMOS SRAM的 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 308K |
| 代理商： | CYC1021B-12VC |
64K x 16 Static RAM
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O
9
to I/O
16
. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1021B is available in standard 44-pin TSOP Type II
and 400-mil-wide SOJ packages.
CY7C1021B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
March 21, 2001
1CY7C1021B
Features
High speed
—t
AA
= 9, 10, 12, 15, 20 ns
CMOS for optimum speed/power
Low active power
—965 mW (max.)
Automatic power-down when deselected
Independent control of upper and lower bits
Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The CY7C1021B is a high-performance CMOS static RAM or-
ganized as 65,536 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
WE
A
15
A
14
A
13
A
NC
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
5
I/O
6
A
4
A
3
A
2
A
1
A
0
OE
BHE
BLE
V
SS
V
CC
I/O
12
I/O
11
I/O
10
I/O
9
A
5
A
6
A
7
I/O
16
I/O
15
I/O
14
I/O
13
CE
I/O
1
I/O
2
I/O
3
I/O
4
NC
A
8
A
9
A
10
A
11
1021B-2
18
19
20
21
27
26
25
24
22
23
NC
I/O
7
I/O
8
64K x 16
RAM Array
512 X 2048
I/O
1
–I/O
8
R
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
A
9
A
1
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
BLE
I/O
9
–I/O
16
OE
WE
A
8
1021B-1
Selection Guide
7C1021B-9
9
175
10
0.5
7C1021B-10
10
150
10
0.5
7C1021B-12
12
140
10
0.5
7C1021B-15
15
130
10
0.5
7C1021B-20
20
120
10
0.5
Maximum Access Time (ns)
Maximum Operating Current (mA) Commercial
Maximum CMOS Standby Current
(mA)
Commercial
Commercial
L
Shaded areas contain preliminary information.
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