- 您現在的位置：買賣IC網 > PDF目錄380221 > CYD01S36V (Cypress Semiconductor Corp.) FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM PDF資料下載
參數資料
| 型號： | CYD01S36V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM |
| 中文描述： | FLEx36 3.3 32K/64K/128K/256K/512 × 36同步雙口RAM |
| 文件頁數： | 1/28頁 |
| 文件大小： | 484K |
| 代理商： | CYD01S36V |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
PRELIMINARY
FLEx36
TM
3.3V 32K/64K/128K/256K/512 x 36
Synchronous Dual-Port RAM
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Cypress Semiconductor Corporation
Document #: 38-06076 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 27, 2005
Features
True dual-ported memory cells that allow simultaneous
access of the same memory location
Synchronous pipelined operation
Family of 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit and 18-Mbit
devices
Pipelined output mode allows fast operation
0.18-micron CMOS for optimum speed and power
High-speed clock to data access
3.3V low power
— Active as low as 225 mA (typ.)
— Standby as low as 55 mA (typ.)
Mailbox function for message passing
Global master reset
Separate byte enables on both ports
Commercial and industrial temperature ranges
IEEE 1149.1-compatible JTAG boundary scan
256-ball FBGA (1-mm pitch)
Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
Counter readback on address lines
Mask register readback on address lines
Dual Chip Enables on both ports for easy depth
expansion
Seamless migration to next-generation dual-port family
Functional Description
The FLEx36 family includes 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit and
18-Mbit pipelined, synchronous, true dual-port static RAMs
that are high-speed, low-power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. A particular port can write to a certain
location while another port is reading that location. The result
of writing to the same location by more than one port at the
same time is undefined. Registers on control, address, and
data lines allow for minimal set-up and hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal Write pulse width is
independent of the duration of the R/W input signal. The
internal Write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CYD18S36V devices in this family has limited features.
Please see Address Counter and Mask Register Opera-
tions
[18]
on page 5 for details.
Seamless Migration to Next-Generation Dual-Port Family
Cypress offers a migration path for all devices in this family to
the next-generation devices in the Dual-Port family with a
compatible footprint. Please contact Cypress Sales for more
details.
Table 1. Product Selection Guide
Density
1 Mbit
(32K x 36)
CYD01S36V
167
4.0
2 Mbit
(64K x 36)
CYD02S36V
167
4.0
4 Mbit
(128K x 36)
CYD04S36V
167
4.0
9 Mbit
(256K x 36)
CYD09S36V
167
4.0
18 Mbit
(512K x 36)
CYD18S36V
133
5.0
Part Number
Max. Speed (MHz)
Max. Access Time – Clock to Data
(ns)
Typical Operating Current (mA)
Package
225
225
225
270
315
256 FBGA
(17 mm x 17 mm)
256 FBGA
(17 mm x 17 mm)
256 FBGA
(17 mm x 17 mm)
256 FBGA
(17 mm x 17 mm)
256 FBGA
(23 mm x 23 mm)
相關PDF資料 |
PDF描述 |
|---|---|
| CYD01S36V-133BBC | FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM |
| CYD01S36V-133BBI | FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM |
| CYD01S36V-167BBC | FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM |
| CYD02S36V-133BBC | FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM |
| CYD02S36V-133BBI | FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CYD01S36V_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FLEx36⑩ 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM |
| CYD01S36V-133BBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM |
| CYD01S36V-133BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FLEx36⑩ 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM |
| CYD01S36V-167BBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FLEx36⑩ 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM |
| CYD02S18V | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FLEx18⑩ 3.3V 64K/128K/256K/512K x 18 Synchronous Dual-Port RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。